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| author | Álvaro Fernández Rojas <noltari@gmail.com> | 2021-02-18 18:04:33 +0100 |
|---|---|---|
| committer | Álvaro Fernández Rojas <noltari@gmail.com> | 2021-02-18 23:42:32 +0100 |
| commit | f07e572f6447465d8938679533d604e402b0f066 (patch) | |
| tree | cb333bd2a67e59e7c07659514850a0fd55fc825e /target/linux/bcm27xx/patches-5.4/950-0446-ARM-dts-bcm2711-Enable-PCIe-controller.patch | |
| parent | 5d3a6fd970619dfc55f8259035c3027d7613a2a6 (diff) | |
| download | upstream-f07e572f6447465d8938679533d604e402b0f066.tar.gz upstream-f07e572f6447465d8938679533d604e402b0f066.tar.bz2 upstream-f07e572f6447465d8938679533d604e402b0f066.zip | |
bcm27xx: import latest patches from the RPi foundation
bcm2708: boot tested on RPi B+ v1.2
bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G
bcm2710: boot tested on RPi 3B v1.2
bcm2711: boot tested on RPi 4B v1.1 4G
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Diffstat (limited to 'target/linux/bcm27xx/patches-5.4/950-0446-ARM-dts-bcm2711-Enable-PCIe-controller.patch')
| -rw-r--r-- | target/linux/bcm27xx/patches-5.4/950-0446-ARM-dts-bcm2711-Enable-PCIe-controller.patch | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/target/linux/bcm27xx/patches-5.4/950-0446-ARM-dts-bcm2711-Enable-PCIe-controller.patch b/target/linux/bcm27xx/patches-5.4/950-0446-ARM-dts-bcm2711-Enable-PCIe-controller.patch new file mode 100644 index 0000000000..9f114c1633 --- /dev/null +++ b/target/linux/bcm27xx/patches-5.4/950-0446-ARM-dts-bcm2711-Enable-PCIe-controller.patch @@ -0,0 +1,56 @@ +From 0ec0bc884f6cf1ec9775c750f78ce28be7da4340 Mon Sep 17 00:00:00 2001 +From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> +Date: Mon, 16 Dec 2019 12:01:08 +0100 +Subject: [PATCH] ARM: dts: bcm2711: Enable PCIe controller + +commit d5c8dc0d4c880fbde5293cc186b1ab23466254c4 upstream. + +This enables bcm2711's PCIe bus, which is hardwired to a VIA +Technologies XHCI USB 3.0 controller. + +Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> +Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> +--- + arch/arm/boot/dts/bcm2711.dtsi | 31 ++++++++++++++++++++++++++++++- + 1 file changed, 30 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/bcm2711.dtsi ++++ b/arch/arm/boot/dts/bcm2711.dtsi +@@ -331,7 +331,36 @@ + #address-cells = <2>; + #size-cells = <1>; + +- ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>; ++ ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, ++ <0x6 0x00000000 0x6 0x00000000 0x40000000>; ++ ++ pcie0: pcie@7d500000 { ++ compatible = "brcm,bcm2711-pcie"; ++ reg = <0x0 0x7d500000 0x9310>; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #interrupt-cells = <1>; ++ #size-cells = <2>; ++ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "pcie", "msi"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 ++ IRQ_TYPE_LEVEL_HIGH>; ++ msi-controller; ++ msi-parent = <&pcie0>; ++ ++ ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 ++ 0x0 0x04000000>; ++ /* ++ * The wrapper around the PCIe block has a bug ++ * preventing it from accessing beyond the first 3GB of ++ * memory. ++ */ ++ dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 ++ 0x0 0xc0000000>; ++ brcm,enable-ssc; ++ }; + + genet: ethernet@7d580000 { + compatible = "brcm,bcm2711-genet-v5"; |