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authorÁlvaro Fernández Rojas <noltari@gmail.com>2022-05-16 23:40:32 +0200
committerÁlvaro Fernández Rojas <noltari@gmail.com>2022-05-17 15:11:22 +0200
commit20ea6adbf199097c4f5f591ffee088340630dae4 (patch)
treed6719d95e136611a1c25bbf7789652d6d402779d /target/linux/bcm27xx/patches-5.15/950-0802-ARM-dts-Enable-PMU-on-Cortex-A72-in-AArch32-state.patch
parentbca05bd072180dc38ef740b37ded9572a6db1981 (diff)
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bcm27xx: add support for linux v5.15
Build system: x86_64 Build-tested: bcm2708, bcm2709, bcm2710, bcm2711 Run-tested: bcm2708/RPiB+, bcm2709/RPi3B, bcm2710/RPi3B, bcm2711/RPi4B Signed-off-by: Marty Jones <mj8263788@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Diffstat (limited to 'target/linux/bcm27xx/patches-5.15/950-0802-ARM-dts-Enable-PMU-on-Cortex-A72-in-AArch32-state.patch')
-rw-r--r--target/linux/bcm27xx/patches-5.15/950-0802-ARM-dts-Enable-PMU-on-Cortex-A72-in-AArch32-state.patch24
1 files changed, 24 insertions, 0 deletions
diff --git a/target/linux/bcm27xx/patches-5.15/950-0802-ARM-dts-Enable-PMU-on-Cortex-A72-in-AArch32-state.patch b/target/linux/bcm27xx/patches-5.15/950-0802-ARM-dts-Enable-PMU-on-Cortex-A72-in-AArch32-state.patch
new file mode 100644
index 0000000000..27a82e789d
--- /dev/null
+++ b/target/linux/bcm27xx/patches-5.15/950-0802-ARM-dts-Enable-PMU-on-Cortex-A72-in-AArch32-state.patch
@@ -0,0 +1,24 @@
+From 80c0520cfe63849639bb0ee4db6f82606ca844cb Mon Sep 17 00:00:00 2001
+From: Ben Avison <bavison@riscosopen.org>
+Date: Wed, 30 Mar 2022 11:43:25 +0100
+Subject: [PATCH] ARM: dts: Enable PMU on Cortex-A72 in AArch32 state
+
+There is no specific AArch32 driver for the Cortex-A72 PMU, but the
+Cortex-A7 one works and is much better than no PMU driver at all.
+
+Signed-off-by: Ben Avison <bavison@riscosopen.org>
+---
+ arch/arm/boot/dts/bcm2711.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/bcm2711.dtsi
++++ b/arch/arm/boot/dts/bcm2711.dtsi
+@@ -445,7 +445,7 @@
+ };
+
+ arm-pmu {
+- compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
++ compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3", "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,