bcm27xx: add support for linux v5.15

Build system: x86_64
Build-tested: bcm2708, bcm2709, bcm2710, bcm2711
Run-tested: bcm2708/RPiB+, bcm2709/RPi3B, bcm2710/RPi3B, bcm2711/RPi4B

Signed-off-by: Marty Jones <mj8263788@gmail.com>
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>

1 files changed, 496 insertions, 0 deletions

diff --git a/target/linux/bcm27xx/patches-5.15/950-0741-drm-vc4-hvs-Use-pointer-to-HVS-in-HVS_READ-and-HVS_W.patch b/target/linux/bcm27xx/patches-5.15/950-0741-drm-vc4-hvs-Use-pointer-to-HVS-in-HVS_READ-and-HVS_W.patch
new file mode 100644
index 0000000000..5be04bd596
--- /dev/null
+++ b/target/linux/bcm27xx/patches-5.15/950-0741-drm-vc4-hvs-Use-pointer-to-HVS-in-HVS_READ-and-HVS_W.patch
@@ -0,0 +1,496 @@
+From 2a2c0889e2695a39ea0479b5ebe30bd8ff8e3f21 Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime@cerno.tech>
+Date: Mon, 14 Feb 2022 17:21:05 +0100
+Subject: [PATCH] drm/vc4: hvs: Use pointer to HVS in HVS_READ and
+ HVS_WRITE macros
+
+Those macros are really about the HVS itself, and thus its associated
+structure vc4_hvs, rather than the entire (virtual) vc4 device.
+
+Let's change those macros to use the hvs pointer directly, and change
+the calling sites accordingly.
+
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+---
+ drivers/gpu/drm/vc4/vc4_crtc.c |  14 +++--
+ drivers/gpu/drm/vc4/vc4_drv.h  |  16 ++---
+ drivers/gpu/drm/vc4/vc4_hvs.c  | 109 +++++++++++++++++----------------
+ drivers/gpu/drm/vc4/vc4_kms.c  |   5 +-
+ 4 files changed, 77 insertions(+), 67 deletions(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_crtc.c
++++ b/drivers/gpu/drm/vc4/vc4_crtc.c
+@@ -70,6 +70,7 @@ static const struct debugfs_reg32 crtc_r
+ static unsigned int
+ vc4_crtc_get_cob_allocation(struct vc4_dev *vc4, unsigned int channel)
+ {
++	struct vc4_hvs *hvs = vc4->hvs;
+ 	u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel));
+ 	/* Top/base are supposed to be 4-pixel aligned, but the
+ 	 * Raspberry Pi firmware fills the low bits (which are
+@@ -89,6 +90,7 @@ static bool vc4_crtc_get_scanout_positio
+ {
+ 	struct drm_device *dev = crtc->dev;
+ 	struct vc4_dev *vc4 = to_vc4_dev(dev);
++	struct vc4_hvs *hvs = vc4->hvs;
+ 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ 	struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
+ 	unsigned int cob_size;
+@@ -123,7 +125,7 @@ static bool vc4_crtc_get_scanout_positio
+ 		*vpos /= 2;
+ 
+ 		/* Use hpos to correct for field offset in interlaced mode. */
+-		if (vc4_hvs_get_fifo_frame_count(dev, vc4_crtc_state->assigned_channel) % 2)
++		if (vc4_hvs_get_fifo_frame_count(hvs, vc4_crtc_state->assigned_channel) % 2)
+ 			*hpos += mode->crtc_htotal / 2;
+ 	}
+ 
+@@ -449,6 +451,7 @@ static void vc4_crtc_config_pv(struct dr
+ static void require_hvs_enabled(struct drm_device *dev)
+ {
+ 	struct vc4_dev *vc4 = to_vc4_dev(dev);
++	struct vc4_hvs *hvs = vc4->hvs;
+ 
+ 	WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
+ 		     SCALER_DISPCTRL_ENABLE);
+@@ -462,6 +465,7 @@ static int vc4_crtc_disable(struct drm_c
+ 	struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
+ 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ 	struct drm_device *dev = crtc->dev;
++	struct vc4_dev *vc4 = to_vc4_dev(dev);
+ 	int ret;
+ 
+ 	CRTC_WRITE(PV_V_CONTROL,
+@@ -491,7 +495,7 @@ static int vc4_crtc_disable(struct drm_c
+ 		vc4_encoder->post_crtc_disable(encoder, state);
+ 
+ 	vc4_crtc_pixelvalve_reset(crtc);
+-	vc4_hvs_stop_channel(dev, channel);
++	vc4_hvs_stop_channel(vc4->hvs, channel);
+ 
+ 	if (vc4_encoder && vc4_encoder->post_crtc_powerdown)
+ 		vc4_encoder->post_crtc_powerdown(encoder, state);
+@@ -517,6 +521,7 @@ static struct drm_encoder *vc4_crtc_get_
+ int vc4_crtc_disable_at_boot(struct drm_crtc *crtc)
+ {
+ 	struct drm_device *drm = crtc->dev;
++	struct vc4_dev *vc4 = to_vc4_dev(drm);
+ 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ 	enum vc4_encoder_type encoder_type;
+ 	const struct vc4_pv_data *pv_data;
+@@ -538,7 +543,7 @@ int vc4_crtc_disable_at_boot(struct drm_
+ 	if (!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN))
+ 		return 0;
+ 
+-	channel = vc4_hvs_get_fifo_from_output(drm, vc4_crtc->data->hvs_output);
++	channel = vc4_hvs_get_fifo_from_output(vc4->hvs, vc4_crtc->data->hvs_output);
+ 	if (channel < 0)
+ 		return 0;
+ 
+@@ -754,6 +759,7 @@ static void vc4_crtc_handle_page_flip(st
+ 	struct drm_crtc *crtc = &vc4_crtc->base;
+ 	struct drm_device *dev = crtc->dev;
+ 	struct vc4_dev *vc4 = to_vc4_dev(dev);
++	struct vc4_hvs *hvs = vc4->hvs;
+ 	u32 chan = vc4_crtc->current_hvs_channel;
+ 	unsigned long flags;
+ 
+@@ -772,7 +778,7 @@ static void vc4_crtc_handle_page_flip(st
+ 		 * the CRTC and encoder already reconfigured, leading to
+ 		 * underruns. This can be seen when reconfiguring the CRTC.
+ 		 */
+-		vc4_hvs_unmask_underrun(dev, chan);
++		vc4_hvs_unmask_underrun(hvs, chan);
+ 	}
+ 	spin_unlock(&vc4_crtc->irq_lock);
+ 	spin_unlock_irqrestore(&dev->event_lock, flags);
+--- a/drivers/gpu/drm/vc4/vc4_drv.h
++++ b/drivers/gpu/drm/vc4/vc4_drv.h
+@@ -603,8 +603,8 @@ to_vc4_crtc_state(struct drm_crtc_state
+ 
+ #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
+ #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
+-#define HVS_READ(offset) readl(vc4->hvs->regs + offset)
+-#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
++#define HVS_READ(offset) readl(hvs->regs + offset)
++#define HVS_WRITE(offset, val) writel(val, hvs->regs + offset)
+ 
+ #define VC4_REG32(reg) { .name = #reg, .offset = reg }
+ 
+@@ -965,17 +965,17 @@ void vc4_irq_reset(struct drm_device *de
+ 
+ /* vc4_hvs.c */
+ extern struct platform_driver vc4_hvs_driver;
+-void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int output);
+-int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output);
+-u8 vc4_hvs_get_fifo_frame_count(struct drm_device *dev, unsigned int fifo);
++void vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int output);
++int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output);
++u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo);
+ int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state);
+ void vc4_hvs_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_state *state);
+ void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state);
+ void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state);
+ void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state);
+-void vc4_hvs_dump_state(struct drm_device *dev);
+-void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel);
+-void vc4_hvs_mask_underrun(struct drm_device *dev, int channel);
++void vc4_hvs_dump_state(struct vc4_hvs *hvs);
++void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel);
++void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel);
+ 
+ /* vc4_kms.c */
+ int vc4_kms_load(struct drm_device *dev);
+--- a/drivers/gpu/drm/vc4/vc4_hvs.c
++++ b/drivers/gpu/drm/vc4/vc4_hvs.c
+@@ -64,22 +64,21 @@ static const struct debugfs_reg32 hvs_re
+ 	VC4_REG32(SCALER_OLEDCOEF2),
+ };
+ 
+-void vc4_hvs_dump_state(struct drm_device *dev)
++void vc4_hvs_dump_state(struct vc4_hvs *hvs)
+ {
+-	struct vc4_dev *vc4 = to_vc4_dev(dev);
+-	struct drm_printer p = drm_info_printer(&vc4->hvs->pdev->dev);
++	struct drm_printer p = drm_info_printer(&hvs->pdev->dev);
+ 	int i;
+ 
+-	drm_print_regset32(&p, &vc4->hvs->regset);
++	drm_print_regset32(&p, &hvs->regset);
+ 
+ 	DRM_INFO("HVS ctx:\n");
+ 	for (i = 0; i < 64; i += 4) {
+ 		DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ 			 i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D",
+-			 readl((u32 __iomem *)vc4->hvs->dlist + i + 0),
+-			 readl((u32 __iomem *)vc4->hvs->dlist + i + 1),
+-			 readl((u32 __iomem *)vc4->hvs->dlist + i + 2),
+-			 readl((u32 __iomem *)vc4->hvs->dlist + i + 3));
++			 readl((u32 __iomem *)hvs->dlist + i + 0),
++			 readl((u32 __iomem *)hvs->dlist + i + 1),
++			 readl((u32 __iomem *)hvs->dlist + i + 2),
++			 readl((u32 __iomem *)hvs->dlist + i + 3));
+ 	}
+ }
+ 
+@@ -100,6 +99,7 @@ static int vc4_hvs_debugfs_dlist(struct
+ 	struct drm_info_node *node = m->private;
+ 	struct drm_device *dev = node->minor->dev;
+ 	struct vc4_dev *vc4 = to_vc4_dev(dev);
++	struct vc4_hvs *hvs = vc4->hvs;
+ 	struct drm_printer p = drm_seq_file_printer(m);
+ 	unsigned int next_entry_start = 0;
+ 	unsigned int i, j;
+@@ -139,6 +139,7 @@ static int vc5_hvs_debugfs_gamma(struct
+ 	struct drm_info_node *node = m->private;
+ 	struct drm_device *dev = node->minor->dev;
+ 	struct vc4_dev *vc4 = to_vc4_dev(dev);
++	struct vc4_hvs *hvs = vc4->hvs;
+ 	struct drm_printer p = drm_seq_file_printer(m);
+ 	unsigned int i, chan;
+ 	u32 dispstat, dispbkgndx;
+@@ -274,11 +275,10 @@ static int vc4_hvs_upload_linear_kernel(
+ 	return 0;
+ }
+ 
+-static void vc4_hvs_lut_load(struct drm_crtc *crtc)
++static void vc4_hvs_lut_load(struct vc4_hvs *hvs,
++			     struct vc4_crtc *vc4_crtc)
+ {
+-	struct drm_device *dev = crtc->dev;
+-	struct vc4_dev *vc4 = to_vc4_dev(dev);
+-	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
++	struct drm_crtc *crtc = &vc4_crtc->base;
+ 	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
+ 	u32 i;
+ 
+@@ -298,11 +298,12 @@ static void vc4_hvs_lut_load(struct drm_
+ 		HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
+ }
+ 
+-static void vc4_hvs_update_gamma_lut(struct drm_crtc *crtc)
++static void vc4_hvs_update_gamma_lut(struct vc4_hvs *hvs,
++				     struct vc4_crtc *vc4_crtc)
+ {
+-	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+-	struct drm_color_lut *lut = crtc->state->gamma_lut->data;
+-	u32 length = drm_color_lut_size(crtc->state->gamma_lut);
++	struct drm_crtc_state *crtc_state = vc4_crtc->base.state;
++	struct drm_color_lut *lut = crtc_state->gamma_lut->data;
++	u32 length = drm_color_lut_size(crtc_state->gamma_lut);
+ 	u32 i;
+ 
+ 	for (i = 0; i < length; i++) {
+@@ -311,10 +312,10 @@ static void vc4_hvs_update_gamma_lut(str
+ 		vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
+ 	}
+ 
+-	vc4_hvs_lut_load(crtc);
++	vc4_hvs_lut_load(hvs, vc4_crtc);
+ }
+ 
+-static void vc5_hvs_write_gamma_entry(struct vc4_dev *vc4,
++static void vc5_hvs_write_gamma_entry(struct vc4_hvs *hvs,
+ 				      u32 offset,
+ 				      struct vc5_gamma_entry *gamma)
+ {
+@@ -322,33 +323,33 @@ static void vc5_hvs_write_gamma_entry(st
+ 	HVS_WRITE(offset + 4, gamma->grad_term);
+ }
+ 
+-static void vc5_hvs_lut_load(struct drm_crtc *crtc)
++static void vc5_hvs_lut_load(struct vc4_hvs *hvs,
++			     struct vc4_crtc *vc4_crtc)
+ {
+-	struct drm_device *dev = crtc->dev;
+-	struct vc4_dev *vc4 = to_vc4_dev(dev);
+-	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+-	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
++	struct drm_crtc_state *crtc_state = vc4_crtc->base.state;
++	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
+ 	u32 i;
+ 	u32 offset = SCALER5_DSPGAMMA_START +
+ 		vc4_state->assigned_channel * SCALER5_DSPGAMMA_CHAN_OFFSET;
+ 
+ 	for (i = 0; i < SCALER5_DSPGAMMA_NUM_POINTS; i++, offset += 8)
+-		vc5_hvs_write_gamma_entry(vc4, offset, &vc4_crtc->pwl_r[i]);
++		vc5_hvs_write_gamma_entry(hvs, offset, &vc4_crtc->pwl_r[i]);
+ 	for (i = 0; i < SCALER5_DSPGAMMA_NUM_POINTS; i++, offset += 8)
+-		vc5_hvs_write_gamma_entry(vc4, offset, &vc4_crtc->pwl_g[i]);
++		vc5_hvs_write_gamma_entry(hvs, offset, &vc4_crtc->pwl_g[i]);
+ 	for (i = 0; i < SCALER5_DSPGAMMA_NUM_POINTS; i++, offset += 8)
+-		vc5_hvs_write_gamma_entry(vc4, offset, &vc4_crtc->pwl_b[i]);
++		vc5_hvs_write_gamma_entry(hvs, offset, &vc4_crtc->pwl_b[i]);
+ 
+ 	if (vc4_state->assigned_channel == 2) {
+ 		/* Alpha only valid on channel 2 */
+ 		for (i = 0; i < SCALER5_DSPGAMMA_NUM_POINTS; i++, offset += 8)
+-			vc5_hvs_write_gamma_entry(vc4, offset, &vc4_crtc->pwl_a[i]);
++			vc5_hvs_write_gamma_entry(hvs, offset, &vc4_crtc->pwl_a[i]);
+ 	}
+ }
+ 
+-static void vc5_hvs_update_gamma_lut(struct drm_crtc *crtc)
++static void vc5_hvs_update_gamma_lut(struct vc4_hvs *hvs,
++				     struct vc4_crtc *vc4_crtc)
+ {
+-	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
++	struct drm_crtc *crtc = &vc4_crtc->base;
+ 	struct drm_color_lut *lut = crtc->state->gamma_lut->data;
+ 	unsigned int step, i;
+ 	u32 start, end;
+@@ -385,12 +386,11 @@ static void vc5_hvs_update_gamma_lut(str
+ 		VC5_HVS_UPDATE_GAMMA_ENTRY_FROM_LUT(pwl_b, blue);
+ 	}
+ 
+-	vc5_hvs_lut_load(crtc);
++	vc5_hvs_lut_load(hvs, vc4_crtc);
+ }
+ 
+-u8 vc4_hvs_get_fifo_frame_count(struct drm_device *dev, unsigned int fifo)
++u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo)
+ {
+-	struct vc4_dev *vc4 = to_vc4_dev(dev);
+ 	u8 field = 0;
+ 
+ 	switch (fifo) {
+@@ -411,13 +411,12 @@ u8 vc4_hvs_get_fifo_frame_count(struct d
+ 	return field;
+ }
+ 
+-int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output)
++int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output)
+ {
+-	struct vc4_dev *vc4 = to_vc4_dev(dev);
+ 	u32 reg;
+ 	int ret;
+ 
+-	if (!vc4->hvs->hvs5)
++	if (!hvs->hvs5)
+ 		return output;
+ 
+ 	switch (output) {
+@@ -464,9 +463,10 @@ int vc4_hvs_get_fifo_from_output(struct
+ 	}
+ }
+ 
+-static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct drm_crtc *crtc,
++static int vc4_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc,
+ 				struct drm_display_mode *mode, bool oneshot)
+ {
++	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ 	struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
+ 	unsigned int chan = vc4_crtc_state->assigned_channel;
+ 	bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
+@@ -484,7 +484,7 @@ static int vc4_hvs_init_channel(struct v
+ 	 */
+ 	dispctrl = SCALER_DISPCTRLX_ENABLE;
+ 
+-	if (!vc4->hvs->hvs5)
++	if (!hvs->hvs5)
+ 		dispctrl |= VC4_SET_FIELD(mode->hdisplay,
+ 					  SCALER_DISPCTRLX_WIDTH) |
+ 			    VC4_SET_FIELD(mode->vdisplay,
+@@ -514,18 +514,16 @@ static int vc4_hvs_init_channel(struct v
+ 	/* Reload the LUT, since the SRAMs would have been disabled if
+ 	 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
+ 	 */
+-	if (!vc4->hvs->hvs5)
+-		vc4_hvs_lut_load(crtc);
++	if (!hvs->hvs5)
++		vc4_hvs_lut_load(hvs, vc4_crtc);
+ 	else
+-		vc5_hvs_lut_load(crtc);
++		vc5_hvs_lut_load(hvs, vc4_crtc);
+ 
+ 	return 0;
+ }
+ 
+-void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int chan)
++void vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan)
+ {
+-	struct vc4_dev *vc4 = to_vc4_dev(dev);
+-
+ 	if (HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_ENABLE)
+ 		return;
+ 
+@@ -623,6 +621,7 @@ static void vc4_hvs_install_dlist(struct
+ {
+ 	struct drm_device *dev = crtc->dev;
+ 	struct vc4_dev *vc4 = to_vc4_dev(dev);
++	struct vc4_hvs *hvs = vc4->hvs;
+ 	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
+ 
+ 	HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
+@@ -679,18 +678,19 @@ void vc4_hvs_atomic_enable(struct drm_cr
+ 
+ 	vc4_hvs_install_dlist(crtc);
+ 	vc4_hvs_update_dlist(crtc);
+-	vc4_hvs_init_channel(vc4, crtc, mode, oneshot);
++	vc4_hvs_init_channel(vc4->hvs, crtc, mode, oneshot);
+ }
+ 
+ void vc4_hvs_atomic_disable(struct drm_crtc *crtc,
+ 			    struct drm_atomic_state *state)
+ {
+ 	struct drm_device *dev = crtc->dev;
++	struct vc4_dev *vc4 = to_vc4_dev(dev);
+ 	struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc);
+ 	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(old_state);
+ 	unsigned int chan = vc4_state->assigned_channel;
+ 
+-	vc4_hvs_stop_channel(dev, chan);
++	vc4_hvs_stop_channel(vc4->hvs, chan);
+ }
+ 
+ void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
+@@ -700,6 +700,8 @@ void vc4_hvs_atomic_flush(struct drm_crt
+ 									 crtc);
+ 	struct drm_device *dev = crtc->dev;
+ 	struct vc4_dev *vc4 = to_vc4_dev(dev);
++	struct vc4_hvs *hvs = vc4->hvs;
++	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ 	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
+ 	unsigned int channel = vc4_state->assigned_channel;
+ 	struct drm_plane *plane;
+@@ -714,7 +716,7 @@ void vc4_hvs_atomic_flush(struct drm_crt
+ 
+ 	if (debug_dump_regs) {
+ 		DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
+-		vc4_hvs_dump_state(dev);
++		vc4_hvs_dump_state(hvs);
+ 	}
+ 
+ 	/* Copy all the active planes' dlist contents to the hardware dlist. */
+@@ -766,10 +768,10 @@ void vc4_hvs_atomic_flush(struct drm_crt
+ 
+ 		if (crtc->state->gamma_lut) {
+ 			if (!vc4->hvs->hvs5) {
+-				vc4_hvs_update_gamma_lut(crtc);
++				vc4_hvs_update_gamma_lut(hvs, vc4_crtc);
+ 				dispbkgndx |= SCALER_DISPBKGND_GAMMA;
+ 			} else {
+-				vc5_hvs_update_gamma_lut(crtc);
++				vc5_hvs_update_gamma_lut(hvs, vc4_crtc);
+ 			}
+ 		} else {
+ 			/* Unsetting DISPBKGND_GAMMA skips the gamma lut step
+@@ -790,13 +792,12 @@ void vc4_hvs_atomic_flush(struct drm_crt
+ 
+ 	if (debug_dump_regs) {
+ 		DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
+-		vc4_hvs_dump_state(dev);
++		vc4_hvs_dump_state(hvs);
+ 	}
+ }
+ 
+-void vc4_hvs_mask_underrun(struct drm_device *dev, int channel)
++void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel)
+ {
+-	struct vc4_dev *vc4 = to_vc4_dev(dev);
+ 	u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
+ 
+ 	dispctrl &= ~SCALER_DISPCTRL_DSPEISLUR(channel);
+@@ -804,9 +805,8 @@ void vc4_hvs_mask_underrun(struct drm_de
+ 	HVS_WRITE(SCALER_DISPCTRL, dispctrl);
+ }
+ 
+-void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel)
++void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel)
+ {
+-	struct vc4_dev *vc4 = to_vc4_dev(dev);
+ 	u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
+ 
+ 	dispctrl |= SCALER_DISPCTRL_DSPEISLUR(channel);
+@@ -828,6 +828,7 @@ static irqreturn_t vc4_hvs_irq_handler(i
+ {
+ 	struct drm_device *dev = data;
+ 	struct vc4_dev *vc4 = to_vc4_dev(dev);
++	struct vc4_hvs *hvs = vc4->hvs;
+ 	irqreturn_t irqret = IRQ_NONE;
+ 	int channel;
+ 	u32 control;
+@@ -840,7 +841,7 @@ static irqreturn_t vc4_hvs_irq_handler(i
+ 		/* Interrupt masking is not always honored, so check it here. */
+ 		if (status & SCALER_DISPSTAT_EUFLOW(channel) &&
+ 		    control & SCALER_DISPCTRL_DSPEISLUR(channel)) {
+-			vc4_hvs_mask_underrun(dev, channel);
++			vc4_hvs_mask_underrun(hvs, channel);
+ 			vc4_hvs_report_underrun(dev);
+ 
+ 			irqret = IRQ_HANDLED;
+--- a/drivers/gpu/drm/vc4/vc4_kms.c
++++ b/drivers/gpu/drm/vc4/vc4_kms.c
+@@ -158,6 +158,7 @@ static u16 vc4_ctm_s31_32_to_s0_9(u64 in
+ static void
+ vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state)
+ {
++	struct vc4_hvs *hvs = vc4->hvs;
+ 	struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state);
+ 	struct drm_color_ctm *ctm = ctm_state->ctm;
+ 
+@@ -234,6 +235,7 @@ vc4_hvs_get_global_state(struct drm_atom
+ static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4,
+ 				     struct drm_atomic_state *state)
+ {
++	struct vc4_hvs *hvs = vc4->hvs;
+ 	struct drm_crtc_state *crtc_state;
+ 	struct drm_crtc *crtc;
+ 	unsigned int i;
+@@ -274,6 +276,7 @@ static void vc4_hvs_pv_muxing_commit(str
+ static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4,
+ 				     struct drm_atomic_state *state)
+ {
++	struct vc4_hvs *hvs = vc4->hvs;
+ 	struct drm_crtc_state *crtc_state;
+ 	struct drm_crtc *crtc;
+ 	unsigned char mux;
+@@ -367,7 +370,7 @@ static void vc4_atomic_commit_tail(struc
+ 			continue;
+ 
+ 		vc4_crtc_state = to_vc4_crtc_state(new_crtc_state);
+-		vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel);
++		vc4_hvs_mask_underrun(hvs, vc4_crtc_state->assigned_channel);
+ 	}
+ 
+ 	for (channel = 0; channel < HVS_NUM_CHANNELS; channel++) {