bcm27xx: add support for linux v5.15

Build system: x86_64
Build-tested: bcm2708, bcm2709, bcm2710, bcm2711
Run-tested: bcm2708/RPiB+, bcm2709/RPi3B, bcm2710/RPi3B, bcm2711/RPi4B

Signed-off-by: Marty Jones <mj8263788@gmail.com>
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>

1 files changed, 66 insertions, 0 deletions

diff --git a/target/linux/bcm27xx/patches-5.15/950-0568-drm-vc4-Enable-gamma-block-only-when-required.patch b/target/linux/bcm27xx/patches-5.15/950-0568-drm-vc4-Enable-gamma-block-only-when-required.patch
new file mode 100644
index 0000000000..3fc546a394
--- /dev/null
+++ b/target/linux/bcm27xx/patches-5.15/950-0568-drm-vc4-Enable-gamma-block-only-when-required.patch
@@ -0,0 +1,66 @@
+From 66d8a98666f29d7f8de926963bd4965aeeb89f13 Mon Sep 17 00:00:00 2001
+From: Dave Stevenson <dave.stevenson@raspberrypi.com>
+Date: Mon, 8 Nov 2021 17:32:45 +0000
+Subject: [PATCH] drm/vc4: Enable gamma block only when required.
+
+With HVS5 the gamma block is now only reprogrammed with
+a disable/enable. Loading the table from vc4_hvs_init_channel
+(called from vc4_hvs_atomic_enable) appears to be at an
+invalid point in time and so isn't applied.
+
+Switch to enabling and disabling the gamma table instead. This
+isn't safe if the pipeline is running, but it isn't now.
+For HVS4 it is safe to enable and disable dynamically, so
+adopt that approach there too.
+
+Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
+---
+ drivers/gpu/drm/vc4/vc4_hvs.c | 22 +++++++++++++++++-----
+ 1 file changed, 17 insertions(+), 5 deletions(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_hvs.c
++++ b/drivers/gpu/drm/vc4/vc4_hvs.c
+@@ -480,8 +480,12 @@ static int vc4_hvs_init_channel(struct v
+ 	dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
+ 	dispbkgndx &= ~SCALER_DISPBKGND_INTERLACE;
+ 
++	if (crtc->state->gamma_lut)
++		/* Enable gamma on if required */
++		dispbkgndx |= SCALER_DISPBKGND_GAMMA;
++
+ 	HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx |
+-		  SCALER_DISPBKGND_AUTOHS | SCALER_DISPBKGND_GAMMA |
++		  SCALER_DISPBKGND_AUTOHS |
+ 		  (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
+ 
+ 	/* Reload the LUT, since the SRAMs would have been disabled if
+@@ -718,17 +722,25 @@ void vc4_hvs_atomic_flush(struct drm_crt
+ 		u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_state->assigned_channel));
+ 
+ 		if (crtc->state->gamma_lut) {
+-			if (!vc4->hvs->hvs5)
++			if (!vc4->hvs->hvs5) {
+ 				vc4_hvs_update_gamma_lut(crtc);
+-			else
++				dispbkgndx |= SCALER_DISPBKGND_GAMMA;
++			} else {
+ 				vc5_hvs_update_gamma_lut(crtc);
+-			dispbkgndx |= SCALER_DISPBKGND_GAMMA;
++			}
+ 		} else {
+ 			/* Unsetting DISPBKGND_GAMMA skips the gamma lut step
+ 			 * in hardware, which is the same as a linear lut that
+ 			 * DRM expects us to use in absence of a user lut.
++			 *
++			 * Do NOT change state dynamically for hvs5 as it
++			 * inserts a delay in the pipeline that will cause
++			 * stalls if enabled/disabled whilst running. The other
++			 * should already be disabling/enabling the pipeline
++			 * when gamma changes.
+ 			 */
+-			dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
++			if (!vc4->hvs->hvs5)
++				dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
+ 		}
+ 		HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel), dispbkgndx);
+ 	}