kernel: Refresh on 5.10.138

Refresh all patches on top of kernel 5.10.138.

The following patches were applied upstream:
 bcm27xx/patches-5.10/950-0311-drm-vc4-Adopt-the-dma-configuration-from-the-HVS-or-.patch
 bcm27xx/patches-5.10/950-0317-vc4_hdmi-Remove-firmware-logic-for-MAI-threshold-set.patch
 bcm27xx/patches-5.10/950-0346-drm-vc4-A-present-but-empty-dmas-disables-audio.patch
 bcm27xx/patches-5.10/950-0354-drm-vc4-Add-the-2711-HVS-as-a-suitable-DMA-node.patch
 bcm27xx/patches-5.10/950-0413-drm-vc4-hdmi-Don-t-access-the-connector-state-in-res.patch
 bcm27xx/patches-5.10/950-0505-vc4-drm-Avoid-full-hdmi-audio-fifo-writes.patch
 bcm27xx/patches-5.10/950-0512-vc4-drm-vc4_plane-Remove-subpixel-positioning-check.patch
 bcm27xx/patches-5.10/950-0560-drm-vc4-drv-Remove-the-DSI-pointer-in-vc4_drv.patch
 bcm27xx/patches-5.10/950-0561-drm-vc4-dsi-Use-snprintf-for-the-PHY-clocks-instead-.patch
 bcm27xx/patches-5.10/950-0562-drm-vc4-dsi-Introduce-a-variant-structure.patch
 bcm27xx/patches-5.10/950-0565-drm-vc4-Correct-pixel-order-for-DSI0.patch
 bcm27xx/patches-5.10/950-0566-drm-vc4-Register-dsi0-as-the-correct-vc4-encoder-typ.patch
 bcm27xx/patches-5.10/950-0567-drm-vc4-Fix-dsi0-interrupt-support.patch
 bcm27xx/patches-5.10/950-0568-drm-vc4-Add-correct-stop-condition-to-vc4_dsi_encode.patch
 bcm27xx/patches-5.10/950-0647-drm-vc4-Fix-timings-for-interlaced-modes.patch
 bcm27xx/patches-5.10/950-0695-drm-vc4-Fix-margin-calculations-for-the-right-bottom.patch

Upstream sets the pixel clock to 340MHz now, do not set it to 600MHz any more.
 bcm27xx/patches-5.10/950-0576-drm-vc4-hdmi-Raise-the-maximum-clock-rate.patch

Fixes: 89956c653252 ("kernel: bump 5.10 to 5.10.138")
Fixes: 4209c33ae27d ("kernel: bump 5.10 to 5.10.137")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

1 files changed, 0 insertions, 83 deletions

diff --git a/target/linux/bcm27xx/patches-5.10/950-0647-drm-vc4-Fix-timings-for-interlaced-modes.patch b/target/linux/bcm27xx/patches-5.10/950-0647-drm-vc4-Fix-timings-for-interlaced-modes.patch
deleted file mode 100644
index 62a4ea3d37..0000000000
--- a/target/linux/bcm27xx/patches-5.10/950-0647-drm-vc4-Fix-timings-for-interlaced-modes.patch
+++ /dev/null
@@ -1,83 +0,0 @@
-From 5afb722d255335954c6b67470e0d261ea5d5ab7a Mon Sep 17 00:00:00 2001
-From: kFYatek <4499762+kFYatek@users.noreply.github.com>
-Date: Wed, 23 Jun 2021 01:11:26 +0200
-Subject: [PATCH] drm/vc4: Fix timings for interlaced modes
-
-Increase the number of post-sync blanking lines on odd fields instead of
-decreasing it on even fields. This makes the total number of lines
-properly match the modelines.
-
-Additionally fix the value of PV_VCONTROL_ODD_DELAY, which did not take
-pixels_per_clock into account, causing some displays to invert the
-fields when driven by bcm2711.
-
-Signed-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>
----
- drivers/gpu/drm/vc4/vc4_crtc.c |  7 ++++---
- drivers/gpu/drm/vc4/vc4_hdmi.c | 12 ++++++------
- 2 files changed, 10 insertions(+), 9 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_crtc.c
-+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
-@@ -342,7 +342,8 @@ static void vc4_crtc_config_pv(struct dr
- 				 PV_HORZB_HACTIVE));
- 
- 	CRTC_WRITE(PV_VERTA,
--		   VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
-+		   VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
-+				 interlace,
- 				 PV_VERTA_VBP) |
- 		   VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
- 				 PV_VERTA_VSYNC));
-@@ -354,7 +355,7 @@ static void vc4_crtc_config_pv(struct dr
- 	if (interlace) {
- 		CRTC_WRITE(PV_VERTA_EVEN,
- 			   VC4_SET_FIELD(mode->crtc_vtotal -
--					 mode->crtc_vsync_end - 1,
-+					 mode->crtc_vsync_end,
- 					 PV_VERTA_VBP) |
- 			   VC4_SET_FIELD(mode->crtc_vsync_end -
- 					 mode->crtc_vsync_start,
-@@ -374,7 +375,7 @@ static void vc4_crtc_config_pv(struct dr
- 			   PV_VCONTROL_CONTINUOUS |
- 			   (is_dsi ? PV_VCONTROL_DSI : 0) |
- 			   PV_VCONTROL_INTERLACE |
--			   VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
-+			   VC4_SET_FIELD(mode->htotal * pixel_rep / (2 * ppc),
- 					 PV_VCONTROL_ODD_DELAY));
- 		CRTC_WRITE(PV_VSYNCD_EVEN, 0);
- 	} else {
---- a/drivers/gpu/drm/vc4/vc4_hdmi.c
-+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -736,12 +736,12 @@ static void vc4_hdmi_set_timings(struct
- 				   VC4_HDMI_VERTA_VFP) |
- 		     VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
- 	u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
--		     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
-+		     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
-+				   interlaced,
- 				   VC4_HDMI_VERTB_VBP));
- 	u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
- 			  VC4_SET_FIELD(mode->crtc_vtotal -
--					mode->crtc_vsync_end -
--					interlaced,
-+					mode->crtc_vsync_end,
- 					VC4_HDMI_VERTB_VBP));
- 
- 	HDMI_WRITE(HDMI_HORZA,
-@@ -782,12 +782,12 @@ static void vc5_hdmi_set_timings(struct
- 				   VC5_HDMI_VERTA_VFP) |
- 		     VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
- 	u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
--		     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
-+		     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
-+				   interlaced,
- 				   VC4_HDMI_VERTB_VBP));
- 	u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
- 			  VC4_SET_FIELD(mode->crtc_vtotal -
--					mode->crtc_vsync_end -
--					interlaced,
-+					mode->crtc_vsync_end,
- 					VC4_HDMI_VERTB_VBP));
- 	unsigned char gcp;
- 	bool gcp_en;