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| author | John Audia <graysky@archlinux.us> | 2022-02-16 09:46:00 -0500 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2022-03-01 21:38:36 +0100 |
| commit | a2d4b5711aa73d14ffbc4f90a7944473b80baecb (patch) | |
| tree | a5a8e558eaa6ea6a93cfec89362b6ed9cb5b1dd1 /target/linux/bcm27xx/patches-5.10/950-0592-drm-vc4-Allow-DBLCLK-modes-even-if-horz-timing-is-od.patch | |
| parent | 02e42f0650a64f29e8e21f7ba0a8ceb366463585 (diff) | |
| download | upstream-a2d4b5711aa73d14ffbc4f90a7944473b80baecb.tar.gz upstream-a2d4b5711aa73d14ffbc4f90a7944473b80baecb.tar.bz2 upstream-a2d4b5711aa73d14ffbc4f90a7944473b80baecb.zip | |
kernel: bump 5.10 to 5.10.101
Removed upstreamed:
pending-5.10/841-USB-serial-option-add-ZTE-MF286D-modem.patch[1]
bcm27xx/950-0592-drm-vc4-Allow-DBLCLK-modes-even-if-horz-timing-is-od.patch[2]
All other patches automatically rebased.
1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.101&id=7113440a36c741efd7c76e3d70b3634100120cdb
2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.101&id=21c890ca8eaecea06cabb92be2a53a6f26f56383
Build system: x86_64
Build-tested: bcm2711/RPi4B, mt7622/RT3200
Run-tested: bcm2711/RPi4B, mt7622/RT3200
Signed-off-by: John Audia <graysky@archlinux.us>
Diffstat (limited to 'target/linux/bcm27xx/patches-5.10/950-0592-drm-vc4-Allow-DBLCLK-modes-even-if-horz-timing-is-od.patch')
| -rw-r--r-- | target/linux/bcm27xx/patches-5.10/950-0592-drm-vc4-Allow-DBLCLK-modes-even-if-horz-timing-is-od.patch | 42 |
1 files changed, 0 insertions, 42 deletions
diff --git a/target/linux/bcm27xx/patches-5.10/950-0592-drm-vc4-Allow-DBLCLK-modes-even-if-horz-timing-is-od.patch b/target/linux/bcm27xx/patches-5.10/950-0592-drm-vc4-Allow-DBLCLK-modes-even-if-horz-timing-is-od.patch deleted file mode 100644 index 459f228c15..0000000000 --- a/target/linux/bcm27xx/patches-5.10/950-0592-drm-vc4-Allow-DBLCLK-modes-even-if-horz-timing-is-od.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 9f7c0728efb0036f6f197126aa62da40cdf4713a Mon Sep 17 00:00:00 2001 -From: Dave Stevenson <dave.stevenson@raspberrypi.com> -Date: Wed, 28 Apr 2021 16:14:21 +0100 -Subject: [PATCH] drm/vc4: Allow DBLCLK modes even if horz timing is - odd. - -The 2711 pixel valve can't produce odd horizontal timings, and -checks were added to vc4_hdmi_encoder_atomic_check and -vc4_hdmi_encoder_mode_valid to filter out/block selection of -such modes. - -Modes with DRM_MODE_FLAG_DBLCLK double all the horizontal timing -values before programming them into the PV. The PV values, -therefore, can not be odd, and so the modes can be supported. - -Amend the filtering appropriately. - -See https://github.com/raspberrypi/linux/issues/4307 - -Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> ---- - drivers/gpu/drm/vc4/vc4_hdmi.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/gpu/drm/vc4/vc4_hdmi.c -+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c -@@ -1067,6 +1067,7 @@ static int vc4_hdmi_encoder_atomic_check - unsigned long long tmds_rate; - - if (vc4_hdmi->variant->unsupported_odd_h_timings && -+ !(mode->flags & DRM_MODE_FLAG_DBLCLK) && - ((mode->hdisplay % 2) || (mode->hsync_start % 2) || - (mode->hsync_end % 2) || (mode->htotal % 2))) - return -EINVAL; -@@ -1111,6 +1112,7 @@ vc4_hdmi_encoder_mode_valid(struct drm_e - struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); - - if (vc4_hdmi->variant->unsupported_odd_h_timings && -+ !(mode->flags & DRM_MODE_FLAG_DBLCLK) && - ((mode->hdisplay % 2) || (mode->hsync_start % 2) || - (mode->hsync_end % 2) || (mode->htotal % 2))) - return MODE_H_ILLEGAL; |