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author | Adrian Schmutzler <freifunk@adrianschmutzler.de> | 2020-02-08 21:58:55 +0100 |
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committer | Adrian Schmutzler <freifunk@adrianschmutzler.de> | 2020-02-14 14:10:51 +0100 |
commit | 7d7aa2fd924c27829ec25f825481554dd81bce97 (patch) | |
tree | 658b87b89331670266163e522ea5fb52535633cb /target/linux/bcm27xx/patches-4.19/950-0349-ASoC-tlv320aic32x4-Move-aosr-and-dosr-setting-to-sep.patch | |
parent | e7bfda2c243e66a75ff966ba04c28b1590b5d24c (diff) | |
download | upstream-7d7aa2fd924c27829ec25f825481554dd81bce97.tar.gz upstream-7d7aa2fd924c27829ec25f825481554dd81bce97.tar.bz2 upstream-7d7aa2fd924c27829ec25f825481554dd81bce97.zip |
brcm2708: rename target to bcm27xx
This change makes the names of Broadcom targets consistent by using
the common notation based on SoC/CPU ID (which is used internally
anyway), bcmXXXX instead of brcmXXXX.
This is even used for target TITLE in make menuconfig already,
only the short target name used brcm so far.
Despite, since subtargets range from bcm2708 to bcm2711, it seems
appropriate to use bcm27xx instead of bcm2708 (again, as already done
for BOARDNAME).
This also renames the packages brcm2708-userland and brcm2708-gpu-fw.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Acked-by: Álvaro Fernández Rojas <noltari@gmail.com>
Diffstat (limited to 'target/linux/bcm27xx/patches-4.19/950-0349-ASoC-tlv320aic32x4-Move-aosr-and-dosr-setting-to-sep.patch')
-rw-r--r-- | target/linux/bcm27xx/patches-4.19/950-0349-ASoC-tlv320aic32x4-Move-aosr-and-dosr-setting-to-sep.patch | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/target/linux/bcm27xx/patches-4.19/950-0349-ASoC-tlv320aic32x4-Move-aosr-and-dosr-setting-to-sep.patch b/target/linux/bcm27xx/patches-4.19/950-0349-ASoC-tlv320aic32x4-Move-aosr-and-dosr-setting-to-sep.patch new file mode 100644 index 0000000000..85b008e5a4 --- /dev/null +++ b/target/linux/bcm27xx/patches-4.19/950-0349-ASoC-tlv320aic32x4-Move-aosr-and-dosr-setting-to-sep.patch @@ -0,0 +1,58 @@ +From a2d8d212b986e4a4ae52c748d246e4c28ebaf1bc Mon Sep 17 00:00:00 2001 +From: Annaliese McDermond <nh6z@nh6z.net> +Date: Thu, 21 Mar 2019 17:58:50 -0700 +Subject: [PATCH] ASoC: tlv320aic32x4: Move aosr and dosr setting to + separate functions + +commit fbafbf6517274a797e6e6508c18dd8dba5920c89 upstream. + +Move these to separate helper functions. This looks cleaner and fits +better with the new clock setting in CCF. + +Signed-off-by: Annaliese McDermond <nh6z@nh6z.net> +Signed-off-by: Mark Brown <broonie@kernel.org> +--- + sound/soc/codecs/tlv320aic32x4.c | 24 +++++++++++++++++------- + 1 file changed, 17 insertions(+), 7 deletions(-) + +--- a/sound/soc/codecs/tlv320aic32x4.c ++++ b/sound/soc/codecs/tlv320aic32x4.c +@@ -720,6 +720,20 @@ static int aic32x4_set_dai_fmt(struct sn + return 0; + } + ++static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr) ++{ ++ return snd_soc_component_write(component, AIC32X4_AOSR, aosr); ++} ++ ++static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr) ++{ ++ snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8); ++ snd_soc_component_write(component, AIC32X4_DOSRLSB, ++ (dosr & 0xff)); ++ ++ return 0; ++} ++ + static int aic32x4_set_processing_blocks(struct snd_soc_component *component, + u8 r_block, u8 p_block) + { +@@ -765,14 +779,10 @@ static int aic32x4_setup_clocks(struct s + clk_set_rate(clocks[4].clk, aic32x4_divs[i].mdac_rate); + clk_set_rate(clocks[5].clk, aic32x4_divs[i].bdiv_rate); + +- aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block); ++ aic32x4_set_aosr(component, aic32x4_divs[i].aosr); ++ aic32x4_set_dosr(component, aic32x4_divs[i].dosr); + +- /* DOSR MSB & LSB values */ +- snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8); +- snd_soc_component_write(component, AIC32X4_DOSRLSB, (aic32x4_divs[i].dosr & 0xff)); +- +- /* AOSR value */ +- snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr); ++ aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block); + + return 0; + } |