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| author | Felix Fietkau <nbd@openwrt.org> | 2015-03-13 03:02:00 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2015-03-13 03:02:00 +0000 |
| commit | dae90fc1300781065357538943552884d682c1ae (patch) | |
| tree | ebcd5c29900fd0ccef87f68b265460e2f8ffea0a /target/linux/atheros/patches-3.18/108-ar2315_gpio.patch | |
| parent | 7a46e008fbcfe5f993fcedb9a0a6b3f0eab8e68a (diff) | |
| download | upstream-dae90fc1300781065357538943552884d682c1ae.tar.gz upstream-dae90fc1300781065357538943552884d682c1ae.tar.bz2 upstream-dae90fc1300781065357538943552884d682c1ae.zip | |
atheros: v3.18: non-functional cleanup
To finally sync code with upsream cleanup registers headers, and update
several comments and kernel config symbols descriptions. No functional
changes.
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
SVN-Revision: 44731
Diffstat (limited to 'target/linux/atheros/patches-3.18/108-ar2315_gpio.patch')
| -rw-r--r-- | target/linux/atheros/patches-3.18/108-ar2315_gpio.patch | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/target/linux/atheros/patches-3.18/108-ar2315_gpio.patch b/target/linux/atheros/patches-3.18/108-ar2315_gpio.patch index dbc22e81b8..5d9785346d 100644 --- a/target/linux/atheros/patches-3.18/108-ar2315_gpio.patch +++ b/target/linux/atheros/patches-3.18/108-ar2315_gpio.patch @@ -2,7 +2,7 @@ +++ b/arch/mips/ath25/Kconfig @@ -7,6 +7,7 @@ config SOC_AR5312 config SOC_AR2315 - bool "Atheros 2315+ support" + bool "Atheros AR2315+ SoC support" depends on ATH25 + select GPIO_AR2315 default y @@ -348,16 +348,16 @@ + #define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S) - #define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */ + #define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */ --- a/arch/mips/ath25/ar2315_regs.h +++ b/arch/mips/ath25/ar2315_regs.h -@@ -322,6 +322,9 @@ - #define AR2315_AMBACLK_CLK_DIV_M 0x0000000c - #define AR2315_AMBACLK_CLK_DIV_S 2 +@@ -315,6 +315,9 @@ + #define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018 + #define AR2315_MEM_CFG_BANKADDR_BITS_S 3 +/* GPIO MMR base address */ +#define AR2315_GPIO 0x0088 + /* - * PCI Clock Control + * Local Bus Interface Registers */ |