diff options
| author | Felix Fietkau <nbd@openwrt.org> | 2014-06-10 09:06:22 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2014-06-10 09:06:22 +0000 |
| commit | 37006f3b3756c398114c8081bc6187dd494e84a6 (patch) | |
| tree | 0412de4de33c4a0bb74426c98dc4d00b5b5c8d8d /target/linux/atheros/patches-3.10 | |
| parent | 91443b20cabdd9a36d8187d0ec88eb287ef08bf9 (diff) | |
| download | upstream-37006f3b3756c398114c8081bc6187dd494e84a6.tar.gz upstream-37006f3b3756c398114c8081bc6187dd494e84a6.tar.bz2 upstream-37006f3b3756c398114c8081bc6187dd494e84a6.zip | |
atheros: shorten lines
Wrap lines over 80 chars or make them shorter by other ways.
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@41095 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/atheros/patches-3.10')
10 files changed, 318 insertions, 262 deletions
diff --git a/target/linux/atheros/patches-3.10/100-board.patch b/target/linux/atheros/patches-3.10/100-board.patch index d223677f54..36d861c3e0 100644 --- a/target/linux/atheros/patches-3.10/100-board.patch +++ b/target/linux/atheros/patches-3.10/100-board.patch @@ -144,8 +144,8 @@ + ar231x_board.radio = addr + 0x10000; + + if (ar231x_board.radio) { -+ /* broken board data detected, use radio data to find the offset, -+ * user will fix this */ ++ /* broken board data detected, use radio data to find the ++ * offset, user will fix this */ + return 1; + } + return 0; @@ -561,7 +561,7 @@ +#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */ --- /dev/null +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h -@@ -0,0 +1,76 @@ +@@ -0,0 +1,79 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive @@ -590,24 +590,27 @@ + return 0; +} + -+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) ++static inline dma_addr_t ++plat_map_dma_mem(struct device *dev, void *addr, size_t size) +{ + return virt_to_phys(addr) + ar231x_dev_offset(dev); +} + -+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) ++static inline dma_addr_t ++plat_map_dma_mem_page(struct device *dev, struct page *page) +{ + return page_to_phys(page) + ar231x_dev_offset(dev); +} + -+static inline unsigned long plat_dma_addr_to_phys(struct device *dev, -+ dma_addr_t dma_addr) ++static inline unsigned long ++plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) +{ + return dma_addr - ar231x_dev_offset(dev); +} + -+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, -+ size_t size, enum dma_data_direction direction) ++static inline void ++plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size, ++ enum dma_data_direction direction) +{ +} + @@ -710,7 +713,7 @@ +#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */ --- /dev/null +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h -@@ -0,0 +1,580 @@ +@@ -0,0 +1,615 @@ +/* + * Register definitions for AR2315+ + * @@ -759,56 +762,88 @@ +#define AR2315_RESET_COLD_APB 0x00000002 +#define AR2315_RESET_COLD_CPU 0x00000004 +#define AR2315_RESET_COLD_CPUWARM 0x00000008 -+#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */ ++#define AR2315_RESET_SYSTEM \ ++ (RESET_COLD_CPU |\ ++ RESET_COLD_APB |\ ++ RESET_COLD_AHB) /* full system */ +#define AR2317_RESET_SYSTEM 0x00000010 + + +#define AR2315_RESET (AR2315_DSLBASE + 0x0004) + -+#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */ -+#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */ -+#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */ -+#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */ -+#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */ -+#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */ -+#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */ -+#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */ -+#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */ -+#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */ -+#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */ -+#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */ ++/* warm reset WLAN0 MAC */ ++#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 ++/* warm reset WLAN0 BaseBand */ ++#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 ++/* warm reset MPEG-TS */ ++#define AR2315_RESET_MPEGTS_RSVD 0x00000004 ++/* warm reset PCI ahb/dma */ ++#define AR2315_RESET_PCIDMA 0x00000008 ++/* warm reset memory controller */ ++#define AR2315_RESET_MEMCTL 0x00000010 ++/* warm reset local bus */ ++#define AR2315_RESET_LOCAL 0x00000020 ++/* warm reset I2C bus */ ++#define AR2315_RESET_I2C_RSVD 0x00000040 ++/* warm reset SPI interface */ ++#define AR2315_RESET_SPI 0x00000080 ++/* warm reset UART0 */ ++#define AR2315_RESET_UART0 0x00000100 ++/* warm reset IR interface */ ++#define AR2315_RESET_IR_RSVD 0x00000200 ++/* cold reset ENET0 phy */ ++#define AR2315_RESET_EPHY0 0x00000400 ++/* cold reset ENET0 mac */ ++#define AR2315_RESET_ENET0 0x00000800 + +/* + * AHB master arbitration control + */ +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008) + -+#define AR2315_ARB_CPU 0x00000001 /* CPU, default */ -+#define AR2315_ARB_WLAN 0x00000002 /* WLAN */ -+#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */ -+#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */ -+#define AR2315_ARB_PCI 0x00000010 /* PCI */ -+#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */ -+#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */ ++/* CPU, default */ ++#define AR2315_ARB_CPU 0x00000001 ++/* WLAN */ ++#define AR2315_ARB_WLAN 0x00000002 ++/* MPEG-TS */ ++#define AR2315_ARB_MPEGTS_RSVD 0x00000004 ++/* LOCAL */ ++#define AR2315_ARB_LOCAL 0x00000008 ++/* PCI */ ++#define AR2315_ARB_PCI 0x00000010 ++/* Ethernet */ ++#define AR2315_ARB_ETHERNET 0x00000020 ++/* retry policy, debug only */ ++#define AR2315_ARB_RETRY 0x00000100 + +/* + * Config Register + */ +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c) + -+#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */ -+#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */ -+#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */ -+#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */ -+#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */ -+#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */ -+#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */ -+ -+#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */ -+#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */ ++/* EC - AHB bridge endianess */ ++#define AR2315_CONFIG_AHB 0x00000001 ++/* WLAN byteswap */ ++#define AR2315_CONFIG_WLAN 0x00000002 ++/* MPEG-TS byteswap */ ++#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 ++/* PCI byteswap */ ++#define AR2315_CONFIG_PCI 0x00000008 ++/* Memory controller endianess */ ++#define AR2315_CONFIG_MEMCTL 0x00000010 ++/* Local bus byteswap */ ++#define AR2315_CONFIG_LOCAL 0x00000020 ++/* Ethernet byteswap */ ++#define AR2315_CONFIG_ETHERNET 0x00000040 ++ ++/* CPU write buffer merge */ ++#define AR2315_CONFIG_MERGE 0x00000200 ++/* CPU big endian */ ++#define AR2315_CONFIG_CPU 0x00000400 +#define AR2315_CONFIG_PCIAHB 0x00000800 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000 -+#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */ ++/* SPI byteswap */ ++#define AR2315_CONFIG_SPI 0x00008000 +#define AR2315_CONFIG_CPU_DRAM 0x00010000 +#define AR2315_CONFIG_CPU_PCI 0x00020000 +#define AR2315_CONFIG_CPU_MMR 0x00040000 @@ -842,7 +877,8 @@ +#define AR2315_IF_DISABLED 0 +#define AR2315_IF_PCI 1 +#define AR2315_IF_TS_LOCAL 2 -+#define AR2315_IF_ALL 3 /* only for emulation with separate pins */ ++/* only for emulation with separate pins */ ++#define AR2315_IF_ALL 3 +#define AR2315_IF_LOCAL_HOST 0x00000008 +#define AR2315_IF_PCI_HOST 0x00000010 +#define AR2315_IF_PCI_INTR 0x00000020 @@ -861,23 +897,23 @@ +#define AR2315_IMR (AR2315_DSLBASE + 0x0024) +#define AR2315_GISR (AR2315_DSLBASE + 0x0028) + -+#define AR2315_ISR_UART0 0x0001 /* high speed UART */ -+#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */ -+#define AR2315_ISR_SPI 0x0004 /* SPI bus */ -+#define AR2315_ISR_AHB 0x0008 /* AHB error */ -+#define AR2315_ISR_APB 0x0010 /* APB error */ -+#define AR2315_ISR_TIMER 0x0020 /* timer */ -+#define AR2315_ISR_GPIO 0x0040 /* GPIO */ -+#define AR2315_ISR_WD 0x0080 /* watchdog */ -+#define AR2315_ISR_IR_RSVD 0x0100 /* IR */ -+ -+#define AR2315_GISR_MISC 0x0001 -+#define AR2315_GISR_WLAN0 0x0002 -+#define AR2315_GISR_MPEGTS_RSVD 0x0004 -+#define AR2315_GISR_LOCALPCI 0x0008 -+#define AR2315_GISR_WMACPOLL 0x0010 -+#define AR2315_GISR_TIMER 0x0020 -+#define AR2315_GISR_ETHERNET 0x0040 ++#define AR2315_ISR_UART0 0x0001 /* high speed UART */ ++#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */ ++#define AR2315_ISR_SPI 0x0004 /* SPI bus */ ++#define AR2315_ISR_AHB 0x0008 /* AHB error */ ++#define AR2315_ISR_APB 0x0010 /* APB error */ ++#define AR2315_ISR_TIMER 0x0020 /* timer */ ++#define AR2315_ISR_GPIO 0x0040 /* GPIO */ ++#define AR2315_ISR_WD 0x0080 /* watchdog */ ++#define AR2315_ISR_IR_RSVD 0x0100 /* IR */ ++ ++#define AR2315_GISR_MISC 0x0001 ++#define AR2315_GISR_WLAN0 0x0002 ++#define AR2315_GISR_MPEGTS_RSVD 0x0004 ++#define AR2315_GISR_LOCALPCI 0x0008 ++#define AR2315_GISR_WMACPOLL 0x0010 ++#define AR2315_GISR_TIMER 0x0020 ++#define AR2315_GISR_ETHERNET 0x0040 + +/* + * Interrupt routing from IO to the processor IP bits @@ -898,9 +934,9 @@ +#define AR2315_WD (AR2315_DSLBASE + 0x0038) +#define AR2315_WDC (AR2315_DSLBASE + 0x003c) + -+#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000 -+#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */ -+#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */ ++#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000 ++#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */ ++#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */ + +/* + * CPU Performance Counters @@ -908,21 +944,21 @@ +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048) +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c) + -+#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */ -+#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */ -+#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */ -+#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */ -+#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */ -+#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */ -+#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */ -+ -+#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */ -+#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */ -+#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */ -+#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */ -+#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */ -+#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */ -+#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */ ++#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */ ++#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */ ++#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */ ++#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */ ++#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */ ++#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */ ++#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */ ++ ++#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */ ++#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */ ++#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */ ++#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */ ++#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */ ++#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */ ++#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */ + +/* + * AHB Error Reporting. @@ -999,20 +1035,21 @@ +#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098) +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0) + -+#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ -+#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */ -+#define AR2315_GPIO_CR_I(x) (0) /* input */ ++#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ ++#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */ ++#define AR2315_GPIO_CR_I(x) (0) /* input */ + -+#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */ -+#define AR2315_GPIO_INT_M (0x3F) /* mask for int */ -+#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */ -+#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */ ++#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */ ++#define AR2315_GPIO_INT_M (0x3F) /* mask for int */ ++#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */ ++#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */ + -+#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */ -+#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */ -+#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */ -+#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */ -+#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */ ++#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for ++ * AR5313_GPIO_INT_* macros */ ++#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */ ++#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */ ++#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */ ++#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */ + +#define AR2315_RESET_GPIO 5 +#define AR2315_NUM_GPIO 22 @@ -1096,7 +1133,7 @@ + * PCI Bus Interface Registers + */ +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008) -+#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ ++#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ + +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c) +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */ @@ -1110,7 +1147,8 @@ +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */ +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */ +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */ -+#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */ ++#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache ++ * disable */ + +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010) + @@ -1152,7 +1190,7 @@ +#define AR2315_PCI_EXT_INT 0x02000000 +#define AR2315_PCI_ABORT_INT 0x04000000 + -+#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */ ++#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */ + +#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508) +#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */ @@ -1170,44 +1208,44 @@ + * Local Bus Interface Registers + */ +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000) -+#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */ -+#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */ -+#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */ -+#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */ -+#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */ -+#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */ -+#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */ -+#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */ -+#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */ -+#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */ -+#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */ -+#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */ -+#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */ -+#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */ -+#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */ -+#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */ -+#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */ -+#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */ -+#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */ -+#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */ -+#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */ -+#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */ -+#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */ -+#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */ -+#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */ ++#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */ ++#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */ ++#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */ ++#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */ ++#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */ ++#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */ ++#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */ ++#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */ ++#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */ ++#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */ ++#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */ ++#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */ ++#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */ ++#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */ ++#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */ ++#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */ ++#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */ ++#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */ ++#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */ ++#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */ ++#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */ ++#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */ ++#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */ ++#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */ ++#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */ + +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004) -+#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */ ++#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */ + +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008) -+#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ ++#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ + +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C) -+#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */ -+#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */ -+#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */ -+#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */ -+#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */ ++#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */ ++#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */ ++#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */ ++#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */ ++#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */ +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80 +#define AR2315_LBM_TIMEOUT_SHFT 7 +#define AR2315_LBM_PORTMUX 0x07000000 @@ -1255,32 +1293,32 @@ +/* + * IR Interface Registers + */ -+#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000) -+ -+#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */ -+ -+#define AR2315_IR_CONTROL (AR2315_IR + 0x0800) -+#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */ -+#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */ -+#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */ -+#define AR2315_IRCTL_SAMPLECLK_SHFT 1 -+#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */ -+#define AR2315_IRCTL_OUTPUTCLK_SHFT 14 -+ -+#define AR2315_IR_STATUS (AR2315_IR + 0x0804) -+#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */ -+#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */ -+ -+#define AR2315_IR_CONFIG (AR2315_IR + 0x0808) -+#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */ -+#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */ -+#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */ -+#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */ -+#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */ -+#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */ -+#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */ -+#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */ -+#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */ ++#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000) ++ ++#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */ ++ ++#define AR2315_IR_CONTROL (AR2315_IR + 0x0800) ++#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */ ++#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */ ++#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */ ++#define AR2315_IRCTL_SAMPLECLK_SHFT 1 ++#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */ ++#define AR2315_IRCTL_OUTPUTCLK_SHFT 14 ++ ++#define AR2315_IR_STATUS (AR2315_IR + 0x0804) ++#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */ ++#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */ ++ ++#define AR2315_IR_CONFIG (AR2315_IR + 0x0808) ++#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */ ++#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */ ++#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */ ++#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 ++#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 ++#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 ++#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 ++#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 ++#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 + +#define HOST_PCI_DEV_ID 3 +#define HOST_PCI_MBAR0 0x10000000 @@ -1517,11 +1555,11 @@ +#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */ + +/* GPIO Control Register bit field definitions */ -+#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ -+#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */ -+#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */ -+#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */ -+#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */ ++#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ ++#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */ ++#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */ ++#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt*/ ++#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */ +#define AR531X_NUM_GPIO 8 + + @@ -1529,7 +1567,7 @@ + --- /dev/null +++ b/arch/mips/ar231x/ar5312.c -@@ -0,0 +1,579 @@ +@@ -0,0 +1,582 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive @@ -1572,7 +1610,8 @@ +static void +ar5312_misc_irq_dispatch(void) +{ -+ unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR); ++ unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ++ ar231x_read_reg(AR531X_IMR); + + if (ar231x_misc_intrs & AR531X_ISR_TIMER) { + do_IRQ(AR531X_MISC_IRQ_TIMER); @@ -1853,10 +1892,12 @@ + + /* Disable other flash banks */ + ar231x_write_reg(AR531X_FLASHCTL1, -+ ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC)); ++ ar231x_read_reg(AR531X_FLASHCTL1) & ++ ~(FLASHCTL_E | FLASHCTL_AC)); + + ar231x_write_reg(AR531X_FLASHCTL2, -+ ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC)); ++ ar231x_read_reg(AR531X_FLASHCTL2) & ++ ~(FLASHCTL_E | FLASHCTL_AC)); + + return (char *)KSEG1ADDR(AR531X_FLASH + 0x800000); +} @@ -2014,7 +2055,7 @@ + * + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier) + * sys_freq = cpu_freq / 4 (used for APB clock, serial, -+ * flash, Timer, Watchdog Timer) ++ * flash, Timer, Watchdog Timer) + * + * cnt_freq = cpu_freq / 2 (use for CPU count/compare) + * @@ -2111,7 +2152,7 @@ + --- /dev/null +++ b/arch/mips/ar231x/ar2315.c -@@ -0,0 +1,693 @@ +@@ -0,0 +1,696 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive @@ -2171,7 +2212,8 @@ + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO); + + /* Enable interrupt with edge detection */ -+ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit)) ++ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != ++ AR2315_GPIO_CR_I(bit)) + return; + + if (bit >= 0) @@ -2197,7 +2239,8 @@ + else if (pending & CAUSEF_IP4) + do_IRQ(AR2315_IRQ_ENET0_INTRS); + else if (pending & CAUSEF_IP2) { -+ unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR); ++ unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ++ ar231x_read_reg(AR2315_IMR); + + if (misc_intr & AR2315_ISR_SPI) + do_IRQ(AR531X_MISC_IRQ_SPI); @@ -2232,7 +2275,8 @@ + unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE; + + /* Enable interrupt with edge detection */ -+ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio)) ++ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != ++ AR2315_GPIO_CR_I(gpio)) + return; + + gpiointmask |= (1 << gpio); @@ -2660,9 +2704,9 @@ + /* try reset the system via reset control */ + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM); + -+ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround. -+ * give it some time to attempt a gpio based hardware reset -+ * (atheros reference design workaround) */ ++ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits ++ * a workaround. Give it some time to attempt a gpio based hardware ++ * reset (atheros reference design workaround) */ + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset"); + mdelay(100); + diff --git a/target/linux/atheros/patches-3.10/105-ar2315_pci.patch b/target/linux/atheros/patches-3.10/105-ar2315_pci.patch index 2f3f8098ce..7a9714f3fa 100644 --- a/target/linux/atheros/patches-3.10/105-ar2315_pci.patch +++ b/target/linux/atheros/patches-3.10/105-ar2315_pci.patch @@ -7,7 +7,7 @@ +obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o --- /dev/null +++ b/arch/mips/ar231x/pci.c -@@ -0,0 +1,229 @@ +@@ -0,0 +1,236 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License @@ -102,7 +102,8 @@ + return config_access(devfn, where, size, value, 0); +} + -+static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) ++static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, ++ int size, u32 value) +{ + return config_access(devfn, where, size, &value, 1); +} @@ -115,7 +116,8 @@ +static struct resource ar231x_mem_resource = { + .name = "AR531x PCI MEM", + .start = AR531X_MEM_BASE, -+ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000, ++ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + ++ 0x4000000, + .flags = IORESOURCE_MEM, +}; + @@ -147,8 +149,10 @@ + /* Clear any pending Abort or external Interrupts + * and enable interrupt processing */ + ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0); -+ ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); -+ ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); ++ ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | ++ AR2315_PCI_EXT_INT)); ++ ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | ++ AR2315_PCI_EXT_INT)); + ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE); + + return 0; @@ -170,10 +174,10 @@ + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2); -+ pci_write_config_dword(dev, PCI_COMMAND, -+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | -+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | -+ PCI_COMMAND_FAST_BACK); ++ pci_write_config_dword(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | ++ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | ++ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | ++ PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK); +} +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup); + @@ -185,10 +189,13 @@ + if (ar231x_devtype != DEV_TYPE_AR2315) + return -ENODEV; + -+ configspace = (unsigned long) ioremap_nocache(AR2315_PCIEXT, 1*1024*1024); /* Remap PCI config space */ ++ /* Remap PCI config space */ ++ configspace = (unsigned long) ioremap_nocache(AR2315_PCIEXT, ++ 1*1024*1024); + ar231x_pci_controller.io_map_base = -+ (unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE); -+ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */ ++ (unsigned long) ioremap_nocache(AR531X_MEM_BASE + ++ AR531X_MEM_SIZE, AR531X_IO_SIZE); ++ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space*/ + + reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA); + msleep(10); @@ -252,7 +259,7 @@ + default y --- a/arch/mips/ar231x/ar2315.c +++ b/arch/mips/ar231x/ar2315.c -@@ -64,6 +64,27 @@ static inline void ar2315_gpio_irq(void) +@@ -65,6 +65,27 @@ static inline void ar2315_gpio_irq(void) do_IRQ(AR531X_GPIO_IRQ_BASE + bit); } @@ -280,7 +287,7 @@ /* * Called when an interrupt is received, this function -@@ -82,6 +103,10 @@ ar2315_irq_dispatch(void) +@@ -83,6 +104,10 @@ ar2315_irq_dispatch(void) do_IRQ(AR2315_IRQ_WLAN0_INTRS); else if (pending & CAUSEF_IP4) do_IRQ(AR2315_IRQ_ENET0_INTRS); @@ -289,5 +296,5 @@ + ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI); +#endif else if (pending & CAUSEF_IP2) { - unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR); - + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & + ar231x_read_reg(AR2315_IMR); diff --git a/target/linux/atheros/patches-3.10/110-ar2313_ethernet.patch b/target/linux/atheros/patches-3.10/110-ar2313_ethernet.patch index 00348c3537..1c9d58b823 100644 --- a/target/linux/atheros/patches-3.10/110-ar2313_ethernet.patch +++ b/target/linux/atheros/patches-3.10/110-ar2313_ethernet.patch @@ -32,7 +32,7 @@ +obj-$(CONFIG_NET_VENDOR_AR231X) += ar231x.o --- /dev/null +++ b/drivers/net/ethernet/ar231x/ar231x.c -@@ -0,0 +1,1257 @@ +@@ -0,0 +1,1254 @@ +/* + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device. + * @@ -159,7 +159,8 @@ +#define VLAN_HDR 0 +#endif + -+#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + RX_OFFSET) ++#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + \ ++ RX_OFFSET) + +#ifdef MODULE +MODULE_LICENSE("GPL"); @@ -177,7 +178,8 @@ +static void ar231x_tx_timeout(struct net_device *dev); + +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum); -+static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value); ++static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, ++ u16 value); +static int ar231x_mdiobus_reset(struct mii_bus *bus); +static int ar231x_mdiobus_probe(struct net_device *dev); +static void ar231x_adjust_link(struct net_device *dev); @@ -254,8 +256,8 @@ + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev); + tasklet_disable(&sp->rx_tasklet); + -+ sp->eth_regs = -+ ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs)); ++ sp->eth_regs = ioremap_nocache(virt_to_phys(ar_eth_base), ++ sizeof(*sp->eth_regs)); + if (!sp->eth_regs) { + printk("Can't remap eth registers\n"); + return -ENXIO; @@ -308,10 +310,8 @@ + return -1; + } + -+ printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n", -+ dev->name, sp->name, -+ dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], -+ dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], dev->irq); ++ printk("%s: %s: %pM, irq %d\n", dev->name, sp->name, dev->dev_addr, ++ dev->irq); + + sp->mii_bus = mdiobus_alloc(); + if (sp->mii_bus == NULL) @@ -442,8 +442,7 @@ + return 0; + } + -+ size = -+ (sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES)); ++ size = sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES); + space = kmalloc(size, GFP_KERNEL); + if (space == NULL) + return 1; @@ -468,9 +467,7 @@ + td->status = 0; + td->devcs = DMA_TX1_CHAINED; + td->addr = 0; -+ td->descr = -+ virt_to_phys(&sp-> -+ tx_ring[(j + 1) & (AR2313_DESCR_ENTRIES - 1)]); ++ td->descr = virt_to_phys(&sp->tx_ring[DSC_NEXT(j)]); + } + + return 0; @@ -571,11 +568,14 @@ + u16 reg; + + sp->link = 1; -+ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMCR); ++ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, ++ MII_BMCR); + if (reg & BMCR_ANENABLE) { + /* auto neg enabled */ -+ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_LPA); -+ duplex = (reg & (LPA_100FULL | LPA_10FULL)) ? 1 : 0; ++ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, ++ MII_LPA); ++ duplex = reg & (LPA_100FULL | LPA_10FULL) ? ++ 1 : 0; + } else { + /* no auto neg, just read duplex config */ + duplex = (reg & BMCR_FULLDPLX) ? 1 : 0; @@ -587,13 +587,13 @@ + if (duplex) { + /* full duplex */ + sp->eth_regs->mac_control = -+ ((sp->eth_regs-> -+ mac_control | MAC_CONTROL_F) & ~MAC_CONTROL_DRO); ++ (sp->eth_regs->mac_control | ++ MAC_CONTROL_F) & ~MAC_CONTROL_DRO; + } else { + /* half duplex */ + sp->eth_regs->mac_control = -+ ((sp->eth_regs-> -+ mac_control | MAC_CONTROL_DRO) & ~MAC_CONTROL_F); ++ (sp->eth_regs->mac_control | ++ MAC_CONTROL_DRO) & ~MAC_CONTROL_F; + } + } else { + /* no link */ @@ -624,10 +624,9 @@ + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE); + + /* enable interrupts */ -+ sp->dma_regs->intr_ena = (DMA_STATUS_AIS | -+ DMA_STATUS_NIS | -+ DMA_STATUS_RI | -+ DMA_STATUS_TI | DMA_STATUS_FBE); ++ sp->dma_regs->intr_ena = DMA_STATUS_AIS | DMA_STATUS_NIS | ++ DMA_STATUS_RI | DMA_STATUS_TI | ++ DMA_STATUS_FBE; + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring); + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring); + sp->dma_regs->control = @@ -648,13 +647,13 @@ + sp->eth_regs->mac_control = flags; + + /* Set all Ethernet station address registers to their initial values */ -+ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF)); ++ ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF); + -+ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | -+ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | -+ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF)); ++ ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | ++ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | ++ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF); + + sp->eth_regs->mac_addr[0] = ethsah; + sp->eth_regs->mac_addr[1] = ethsal; @@ -787,9 +786,7 @@ + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | + DMA_RX1_CHAINED); + rd->addr = virt_to_phys(skb->data); -+ rd->descr = -+ virt_to_phys(&sp-> -+ rx_ring[(idx + 1) & (AR2313_DESCR_ENTRIES - 1)]); ++ rd->descr = virt_to_phys(&sp->rx_ring[DSC_NEXT(idx)]); + rd->status = DMA_RX_OWN; + + idx = DSC_NEXT(idx); @@ -849,12 +846,13 @@ + + } else { + /* alloc new buffer. */ -+ skb_new = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE); ++ skb_new = netdev_alloc_skb_ip_align(dev, ++ AR2313_BUFSIZE); + if (skb_new != NULL) { + skb = sp->rx_skb[idx]; + /* set skb */ -+ skb_put(skb, -+ ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN); ++ skb_put(skb, ((status >> DMA_RX_LEN_SHIFT) & ++ 0x3fff) - CRC_LEN); + + dev->stats.rx_bytes += skb->len; + skb->protocol = eth_type_trans(skb, dev); @@ -905,8 +903,8 @@ + } + /* done with this descriptor */ + dma_unmap_single(NULL, txdesc->addr, -+ txdesc->devcs & DMA_TX1_BSIZE_MASK, -+ DMA_TO_DEVICE); ++ txdesc->devcs & DMA_TX1_BSIZE_MASK, ++ DMA_TO_DEVICE); + txdesc->status = 0; + + if (status & DMA_TX_ERROR) { @@ -918,9 +916,8 @@ + dev->stats.tx_heartbeat_errors++; + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK)) + dev->stats.tx_carrier_errors++; -+ if (status & (DMA_TX_ERR_LATE | -+ DMA_TX_ERR_COL | -+ DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER)) ++ if (status & (DMA_TX_ERR_LATE | DMA_TX_ERR_COL | ++ DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER)) + dev->stats.tx_aborted_errors++; + } else { + /* transmit OK */ @@ -1009,13 +1006,13 @@ + unsigned int ethsal, ethsah; + + /* reset the hardware, in case the MAC address changed */ -+ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF)); ++ ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF); + -+ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | -+ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | -+ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF)); ++ ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | ++ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | ++ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF); + + sp->eth_regs->mac_addr[0] = ethsah; + sp->eth_regs->mac_addr[1] = ethsal; @@ -1049,7 +1046,7 @@ + + /* kill the MAC */ + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */ -+ MAC_CONTROL_TE); /* disable Transmits */ ++ MAC_CONTROL_TE); /* disable Transmits */ + /* stop dma */ + sp->dma_regs->control = 0; + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR; @@ -1260,8 +1257,8 @@ + BUG_ON(!phydev); + BUG_ON(phydev->attached_dev); + -+ phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, 0, -+ PHY_INTERFACE_MODE_MII); ++ phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, ++ 0, PHY_INTERFACE_MODE_MII); + + if (IS_ERR(phydev)) { + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); @@ -1400,13 +1397,13 @@ +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */ +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */ +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */ -+#define MAC_CONTROL_PR BIT(18) /* promiscuous mode (valid frames only) */ ++#define MAC_CONTROL_PR BIT(18) /* promis mode (valid frames only) */ +#define MAC_CONTROL_PM BIT(19) /* pass multicast */ +#define MAC_CONTROL_F BIT(20) /* full-duplex */ +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */ +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */ +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */ -+#define MAC_CONTROL_RA BIT(31) /* receive all (valid and invalid frames) */ ++#define MAC_CONTROL_RA BIT(31) /* rcv all (valid and invalid frames) */ + +#define MII_ADDR_BUSY BIT(0) +#define MII_ADDR_WRITE BIT(1) @@ -1549,7 +1546,7 @@ + + + struct timer_list link_timer; -+ unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */ ++ unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */ + unsigned short mac; + unsigned short link; /* 0 - link down, 1 - link up */ + u16 phy_data; diff --git a/target/linux/atheros/patches-3.10/120-spiflash.patch b/target/linux/atheros/patches-3.10/120-spiflash.patch index 7f8acd095e..635da886ad 100644 --- a/target/linux/atheros/patches-3.10/120-spiflash.patch +++ b/target/linux/atheros/patches-3.10/120-spiflash.patch @@ -23,7 +23,7 @@ --- /dev/null +++ b/drivers/mtd/devices/ar2315.c -@@ -0,0 +1,519 @@ +@@ -0,0 +1,525 @@ + +/* + * MTD driver for the SPI Flash Memory support on Atheros AR2315 @@ -91,11 +91,16 @@ + +const struct flashconfig flashconfig_tbl[] = { + [FLASH_NONE] = { 0, 0, 0}, -+ [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE}, -+ [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE}, -+ [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE}, -+ [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE}, -+ [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE} ++ [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, ++ STM_1MB_SECTOR_SIZE}, ++ [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, ++ STM_2MB_SECTOR_SIZE}, ++ [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, ++ STM_4MB_SECTOR_SIZE}, ++ [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, ++ STM_8MB_SECTOR_SIZE}, ++ [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, ++ STM_16MB_SECTOR_SIZE} +}; + +/* Mapping of generic opcodes to STM serial flash opcodes */ @@ -152,7 +157,7 @@ + FL_WRITING +}; + -+/***************************************************************************************************/ ++/*****************************************************************************/ + +static u32 +spiflash_read_reg(struct spiflash_priv *priv, int reg) @@ -468,7 +473,8 @@ + goto error; + } + -+ priv->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt); ++ priv->readaddr = ioremap_nocache(SPI_FLASH_READ, ++ flashconfig_tbl[index].byte_cnt); + if (!priv->readaddr) { + dev_warn(&pdev->dev, SPIFLASH "Failed to map flash device\n"); + goto error; diff --git a/target/linux/atheros/patches-3.10/130-watchdog.patch b/target/linux/atheros/patches-3.10/130-watchdog.patch index 4b395006b8..100dfa6580 100644 --- a/target/linux/atheros/patches-3.10/130-watchdog.patch +++ b/target/linux/atheros/patches-3.10/130-watchdog.patch @@ -1,6 +1,6 @@ --- /dev/null +++ b/drivers/watchdog/ar2315-wtd.c -@@ -0,0 +1,197 @@ +@@ -0,0 +1,198 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by @@ -54,7 +54,8 @@ +} + +static ssize_t -+ar2315_wdt_write(struct file *file, const char __user *data, size_t len, loff_t *ppos) ++ar2315_wdt_write(struct file *file, const char __user *data, size_t len, ++ loff_t *ppos) +{ + if (len) + ar2315_wdt_enable(); diff --git a/target/linux/atheros/patches-3.10/140-redboot_boardconfig.patch b/target/linux/atheros/patches-3.10/140-redboot_boardconfig.patch index 678d7ec3c3..98dbf52611 100644 --- a/target/linux/atheros/patches-3.10/140-redboot_boardconfig.patch +++ b/target/linux/atheros/patches-3.10/140-redboot_boardconfig.patch @@ -17,12 +17,13 @@ int nrparts = 0; struct fis_image_desc *buf; struct mtd_partition *parts; -@@ -225,14 +228,14 @@ static int parse_redboot_partitions(stru +@@ -225,14 +228,15 @@ static int parse_redboot_partitions(stru } } #endif - parts = kzalloc(sizeof(*parts)*nrparts + nulllen + namelen, GFP_KERNEL); -+ parts = kzalloc(sizeof(*parts) * (nrparts + 1) + nulllen + namelen + sizeof(BOARD_CONFIG_PART), GFP_KERNEL); ++ parts = kzalloc(sizeof(*parts) * (nrparts + 1) + nulllen + namelen + ++ sizeof(BOARD_CONFIG_PART), GFP_KERNEL); if (!parts) { ret = -ENOMEM; @@ -34,7 +35,7 @@ #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED if (nulllen > 0) { strcpy(nullname, nullstring); -@@ -251,6 +254,8 @@ static int parse_redboot_partitions(stru +@@ -251,6 +255,8 @@ static int parse_redboot_partitions(stru } #endif for ( ; i<nrparts; i++) { @@ -43,7 +44,7 @@ parts[i].size = fl->img->size; parts[i].offset = fl->img->flash_base; parts[i].name = names; -@@ -284,6 +289,13 @@ static int parse_redboot_partitions(stru +@@ -284,6 +290,13 @@ static int parse_redboot_partitions(stru fl = fl->next; kfree(tmp_fl); } diff --git a/target/linux/atheros/patches-3.10/141-redboot_partition_scan.patch b/target/linux/atheros/patches-3.10/141-redboot_partition_scan.patch index 4db94a161b..d1d281eaf4 100644 --- a/target/linux/atheros/patches-3.10/141-redboot_partition_scan.patch +++ b/target/linux/atheros/patches-3.10/141-redboot_partition_scan.patch @@ -35,7 +35,7 @@ if (i == numslots) { /* Didn't find it */ + if (offset + master->erasesize < master->size) { -+ /* not at the end of the flash yet, maybe next block :) */ ++ /* not at the end of the flash yet, maybe next block */ + directory++; + goto restart; + } diff --git a/target/linux/atheros/patches-3.10/142-redboot_various_erase_size_fix.patch b/target/linux/atheros/patches-3.10/142-redboot_various_erase_size_fix.patch index 55de500ea9..e1b0a89905 100644 --- a/target/linux/atheros/patches-3.10/142-redboot_various_erase_size_fix.patch +++ b/target/linux/atheros/patches-3.10/142-redboot_various_erase_size_fix.patch @@ -43,7 +43,7 @@ struct fis_list *new_fl, **prev; if (buf[i].name[0] == 0xff) { -@@ -261,12 +281,13 @@ static int parse_redboot_partitions(stru +@@ -262,12 +282,13 @@ static int parse_redboot_partitions(stru } #endif for ( ; i<nrparts; i++) { @@ -59,7 +59,7 @@ strcpy(names, fl->img->name); #ifdef CONFIG_MTD_REDBOOT_PARTS_READONLY if (!memcmp(names, "RedBoot", 8) || -@@ -296,7 +317,9 @@ static int parse_redboot_partitions(stru +@@ -297,7 +318,9 @@ static int parse_redboot_partitions(stru fl = fl->next; kfree(tmp_fl); } diff --git a/target/linux/atheros/patches-3.10/220-enet_micrel_workaround.patch b/target/linux/atheros/patches-3.10/220-enet_micrel_workaround.patch index 66832d5dc6..2cc31e1cd2 100644 --- a/target/linux/atheros/patches-3.10/220-enet_micrel_workaround.patch +++ b/target/linux/atheros/patches-3.10/220-enet_micrel_workaround.patch @@ -1,6 +1,6 @@ --- a/drivers/net/ethernet/ar231x/ar231x.c +++ b/drivers/net/ethernet/ar231x/ar231x.c -@@ -146,6 +146,7 @@ static int ar231x_mdiobus_write(struct m +@@ -148,6 +148,7 @@ static int ar231x_mdiobus_write(struct m static int ar231x_mdiobus_reset(struct mii_bus *bus); static int ar231x_mdiobus_probe(struct net_device *dev); static void ar231x_adjust_link(struct net_device *dev); @@ -8,7 +8,7 @@ #ifndef ERR #define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args) -@@ -178,6 +179,32 @@ static const struct net_device_ops ar231 +@@ -180,6 +181,32 @@ static const struct net_device_ops ar231 #endif }; @@ -78,7 +78,7 @@ kfree(dev); return 0; } -@@ -1111,6 +1157,9 @@ static int ar231x_ioctl(struct net_devic +@@ -1108,6 +1154,9 @@ static int ar231x_ioctl(struct net_devic struct ar231x_private *sp = netdev_priv(dev); int ret; diff --git a/target/linux/atheros/patches-3.10/230-3_10-updates.patch b/target/linux/atheros/patches-3.10/230-3_10-updates.patch index f1adf82461..ef273b5e17 100644 --- a/target/linux/atheros/patches-3.10/230-3_10-updates.patch +++ b/target/linux/atheros/patches-3.10/230-3_10-updates.patch @@ -1,11 +1,11 @@ --- a/drivers/net/ethernet/ar231x/ar231x.c +++ b/drivers/net/ethernet/ar231x/ar231x.c -@@ -1274,7 +1274,7 @@ static int ar231x_mdiobus_probe(struct n - BUG_ON(!phydev); +@@ -1272,7 +1272,7 @@ static int ar231x_mdiobus_probe(struct n BUG_ON(phydev->attached_dev); -- phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, 0, -+ phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, - PHY_INTERFACE_MODE_MII); + phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, +- 0, PHY_INTERFACE_MODE_MII); ++ PHY_INTERFACE_MODE_MII); if (IS_ERR(phydev)) { + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); |