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author | Felix Fietkau <nbd@openwrt.org> | 2009-03-22 14:46:58 +0000 |
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committer | Felix Fietkau <nbd@openwrt.org> | 2009-03-22 14:46:58 +0000 |
commit | b1c3c083049c94ad6f660795779c5e1e0bc8dcab (patch) | |
tree | 0c06af302c9c26ed1899ffb67994222548e18269 /target/linux/atheros/patches-2.6.28/002-mips_clocksource_init_war.patch | |
parent | 66fddadb61ce210287ba8b753b8137b3f4f41401 (diff) | |
download | upstream-b1c3c083049c94ad6f660795779c5e1e0bc8dcab.tar.gz upstream-b1c3c083049c94ad6f660795779c5e1e0bc8dcab.tar.bz2 upstream-b1c3c083049c94ad6f660795779c5e1e0bc8dcab.zip |
atheros: clean up the 2.6.28 port in preparation for pushing it upstream
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@14967 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/atheros/patches-2.6.28/002-mips_clocksource_init_war.patch')
-rw-r--r-- | target/linux/atheros/patches-2.6.28/002-mips_clocksource_init_war.patch | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/target/linux/atheros/patches-2.6.28/002-mips_clocksource_init_war.patch b/target/linux/atheros/patches-2.6.28/002-mips_clocksource_init_war.patch new file mode 100644 index 0000000000..03a66ff133 --- /dev/null +++ b/target/linux/atheros/patches-2.6.28/002-mips_clocksource_init_war.patch @@ -0,0 +1,56 @@ +--- a/arch/mips/kernel/cevt-r4k.c ++++ b/arch/mips/kernel/cevt-r4k.c +@@ -15,6 +15,22 @@ + #include <asm/cevt-r4k.h> + + /* ++ * Compare interrupt can be routed and latched outside the core, ++ * so a single execution hazard barrier may not be enough to give ++ * it time to clear as seen in the Cause register. 4 time the ++ * pipeline depth seems reasonably conservative, and empirically ++ * works better in configurations with high CPU/bus clock ratios. ++ */ ++ ++#define compare_change_hazard() \ ++ do { \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ } while (0) ++ ++/* + * The SMTC Kernel for the 34K, 1004K, et. al. replaces several + * of these routines with SMTC-specific variants. + */ +@@ -30,6 +46,7 @@ static int mips_next_event(unsigned long + cnt = read_c0_count(); + cnt += delta; + write_c0_compare(cnt); ++ compare_change_hazard(); + res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; + return res; + } +@@ -99,22 +116,6 @@ static int c0_compare_int_pending(void) + return (read_c0_cause() >> cp0_compare_irq) & 0x100; + } + +-/* +- * Compare interrupt can be routed and latched outside the core, +- * so a single execution hazard barrier may not be enough to give +- * it time to clear as seen in the Cause register. 4 time the +- * pipeline depth seems reasonably conservative, and empirically +- * works better in configurations with high CPU/bus clock ratios. +- */ +- +-#define compare_change_hazard() \ +- do { \ +- irq_disable_hazard(); \ +- irq_disable_hazard(); \ +- irq_disable_hazard(); \ +- irq_disable_hazard(); \ +- } while (0) +- + int c0_compare_int_usable(void) + { + unsigned int delta; |