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authorFelix Fietkau <nbd@openwrt.org>2007-03-27 23:15:10 +0000
committerFelix Fietkau <nbd@openwrt.org>2007-03-27 23:15:10 +0000
commit1bde611b1ae4a91ba04d4c4c1c630ab0ffe1b002 (patch)
tree9043976343719c7f58d721e586fa6079e2cf14a7 /target/linux/atheros-2.6
parentc05a061e4ea5e6c031ee9b48d06899cacd595dbe (diff)
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fix flash buswidth detection
SVN-Revision: 6727
Diffstat (limited to 'target/linux/atheros-2.6')
-rw-r--r--target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.c b/target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.c
index 384020b27e..57d56eb0e5 100644
--- a/target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.c
+++ b/target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.c
@@ -255,13 +255,13 @@ int __init ar5312_init_devices(void)
ar5312_eth0_data.board_config = board_config;
ar5312_eth1_data.board_config = board_config;
- /* fixup flash width; TODO: constants -> defines */
- fctl = sysRegRead(AR531X_FLASHCTL) & 0x30000000;
+ /* fixup flash width */
+ fctl = sysRegRead(AR531X_FLASHCTL) & FLASHCTL_MW;
switch (fctl) {
- case 0x20000000:
+ case FLASHCTL_MWx16:
ar5312_flash_data.width = 2;
break;
- case 0x00000000:
+ case FLASHCTL_MWx8:
default:
ar5312_flash_data.width = 1;
break;