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| author | David Bauer <mail@david-bauer.net> | 2022-03-27 23:12:39 +0200 |
|---|---|---|
| committer | David Bauer <mail@david-bauer.net> | 2022-03-30 17:28:39 +0200 |
| commit | 9a0155bc4fa3642cdf930d50098bc929173f170f (patch) | |
| tree | 3e1387b63be3e1fc8124d5b447d35b1d6273fcc7 /target/linux/ath79/patches-5.15/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch | |
| parent | fc94c0d203d1c97d3dfdd045fb57b1cb7826e491 (diff) | |
| download | upstream-9a0155bc4fa3642cdf930d50098bc929173f170f.tar.gz upstream-9a0155bc4fa3642cdf930d50098bc929173f170f.tar.bz2 upstream-9a0155bc4fa3642cdf930d50098bc929173f170f.zip | |
ath79: add 5.15 support for generic subtarget
Add Kernel 5.15 patches + config. This is currently only available for
the generic subtarget, as it was exclusively tested with this target.
Tested-on: Siemens WS-AP3610, Enterasys WS-AP3705i
Signed-off-by: David Bauer <mail@david-bauer.net>
Diffstat (limited to 'target/linux/ath79/patches-5.15/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch')
| -rw-r--r-- | target/linux/ath79/patches-5.15/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch | 98 |
1 files changed, 98 insertions, 0 deletions
diff --git a/target/linux/ath79/patches-5.15/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch b/target/linux/ath79/patches-5.15/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch new file mode 100644 index 0000000000..924faec509 --- /dev/null +++ b/target/linux/ath79/patches-5.15/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch @@ -0,0 +1,98 @@ +--- /dev/null ++++ b/arch/mips/include/asm/mach-ath79/mangle-port.h +@@ -0,0 +1,37 @@ ++/* ++ * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org> ++ * ++ * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h ++ * Copyright (C) 2003, 2004 Ralf Baechle ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H ++#define __ASM_MACH_ATH79_MANGLE_PORT_H ++ ++#ifdef CONFIG_PCI_AR71XX ++extern unsigned long (ath79_pci_swizzle_b)(unsigned long port); ++extern unsigned long (ath79_pci_swizzle_w)(unsigned long port); ++#else ++#define ath79_pci_swizzle_b(port) (port) ++#define ath79_pci_swizzle_w(port) (port) ++#endif ++ ++#define __swizzle_addr_b(port) ath79_pci_swizzle_b(port) ++#define __swizzle_addr_w(port) ath79_pci_swizzle_w(port) ++#define __swizzle_addr_l(port) (port) ++#define __swizzle_addr_q(port) (port) ++ ++# define ioswabb(a, x) (x) ++# define __mem_ioswabb(a, x) (x) ++# define ioswabw(a, x) (x) ++# define __mem_ioswabw(a, x) cpu_to_le16(x) ++# define ioswabl(a, x) (x) ++# define __mem_ioswabl(a, x) cpu_to_le32(x) ++# define ioswabq(a, x) (x) ++# define __mem_ioswabq(a, x) cpu_to_le64(x) ++ ++#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */ +--- a/arch/mips/pci/pci-ar71xx.c ++++ b/arch/mips/pci/pci-ar71xx.c +@@ -68,6 +68,45 @@ static const u32 ar71xx_pci_read_mask[8] + 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 + }; + ++static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port); ++static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port); ++ ++static inline bool ar71xx_is_pci_addr(unsigned long port) ++{ ++ unsigned long phys = CPHYSADDR(port); ++ ++ return (phys >= AR71XX_PCI_MEM_BASE && ++ phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE); ++} ++ ++static unsigned long ar71xx_pci_swizzle_b(unsigned long port) ++{ ++ return ar71xx_is_pci_addr(port) ? port ^ 3 : port; ++} ++ ++static unsigned long ar71xx_pci_swizzle_w(unsigned long port) ++{ ++ return ar71xx_is_pci_addr(port) ? port ^ 2 : port; ++} ++ ++unsigned long ath79_pci_swizzle_b(unsigned long port) ++{ ++ if (__ath79_pci_swizzle_b) ++ return __ath79_pci_swizzle_b(port); ++ ++ return port; ++} ++EXPORT_SYMBOL(ath79_pci_swizzle_b); ++ ++unsigned long ath79_pci_swizzle_w(unsigned long port) ++{ ++ if (__ath79_pci_swizzle_w) ++ return __ath79_pci_swizzle_w(port); ++ ++ return port; ++} ++EXPORT_SYMBOL(ath79_pci_swizzle_w); ++ + static inline u32 ar71xx_pci_get_ble(int where, int size, int local) + { + u32 t; +@@ -276,6 +315,9 @@ static int ar71xx_pci_probe(struct platf + + register_pci_controller(&apc->pci_ctrl); + ++ __ath79_pci_swizzle_b = ar71xx_pci_swizzle_b; ++ __ath79_pci_swizzle_w = ar71xx_pci_swizzle_w; ++ + return 0; + } + |