ath79: add support for linux 4.19

The following patches are dropped because they are merged upstream:
-0001-tty-serial-drop-QCA-pecific-SoC-symbols.patch
-0006-usb-drop-deprecated-symbols.patch
-0009-MIPS-ath79-add-lots-of-missing-registers.patch
-0010-MIPS-ath79-add-support-for-QCA953x-QCA956x-TP9343.patch
-0014-MIPS-ath79-finetune-cpu-overrides.patch
-0015-MIPS-ath79-enable-uart-during-early_prink.patch
-0016-MIPS-ath79-get-PCIe-controller-out-of-reset.patch

This patch is dropped due to the introduction of spi-mem framework:
-461-spi-ath79-add-fast-flash-read.patch

Thank to Michael Marley @mamarley for his work on this patch:
-910-unaligned_access_hacks.patch

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
[synchronized kernel config with make kernel_oldconfig]
Signed-off-by: Petr Štetiar <ynezz@true.cz>

1 files changed, 114 insertions, 0 deletions

diff --git a/target/linux/ath79/patches-4.19/0022-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch b/target/linux/ath79/patches-4.19/0022-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch
new file mode 100644
index 0000000000..389edc45a8
--- /dev/null
+++ b/target/linux/ath79/patches-4.19/0022-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch
@@ -0,0 +1,114 @@
+From 339c191a95e978353c9ba3aafab0261e14de109b Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 6 Mar 2018 13:22:43 +0100
+Subject: [PATCH 22/33] MIPS: ath79: move legacy "wdt" and "uart" clock aliases
+ out of soc init
+
+Preparation for reusing functions for DT
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/ath79/clock.c | 38 +++++++++++++++++---------------------
+ 1 file changed, 17 insertions(+), 21 deletions(-)
+
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -110,9 +110,6 @@ static void __init ar71xx_clocks_init(vo
+ 	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+-
+-	clk_add_alias("wdt", NULL, "ahb", NULL);
+-	clk_add_alias("uart", NULL, "ahb", NULL);
+ }
+ 
+ static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
+@@ -140,9 +137,6 @@ static void __init ar724x_clocks_init(vo
+ 	ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
+ 
+ 	ar724x_clk_init(ref_clk, ath79_pll_base);
+-
+-	clk_add_alias("wdt", NULL, "ahb", NULL);
+-	clk_add_alias("uart", NULL, "ahb", NULL);
+ }
+ 
+ static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
+@@ -218,9 +212,6 @@ static void __init ar933x_clocks_init(vo
+ 	ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
+ 
+ 	ar9330_clk_init(ref_clk, ath79_pll_base);
+-
+-	clk_add_alias("wdt", NULL, "ahb", NULL);
+-	clk_add_alias("uart", NULL, "ref", NULL);
+ }
+ 
+ static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
+@@ -353,9 +344,6 @@ static void __init ar934x_clocks_init(vo
+ 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+ 
+-	clk_add_alias("wdt", NULL, "ref", NULL);
+-	clk_add_alias("uart", NULL, "ref", NULL);
+-
+ 	iounmap(dpll_base);
+ }
+ 
+@@ -439,9 +427,6 @@ static void __init qca953x_clocks_init(v
+ 	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+-
+-	clk_add_alias("wdt", NULL, "ref", NULL);
+-	clk_add_alias("uart", NULL, "ref", NULL);
+ }
+ 
+ static void __init qca955x_clocks_init(void)
+@@ -524,9 +509,6 @@ static void __init qca955x_clocks_init(v
+ 	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+-
+-	clk_add_alias("wdt", NULL, "ref", NULL);
+-	clk_add_alias("uart", NULL, "ref", NULL);
+ }
+ 
+ static void __init qca956x_clocks_init(void)
+@@ -628,13 +610,13 @@ static void __init qca956x_clocks_init(v
+ 	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ 	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+-
+-	clk_add_alias("wdt", NULL, "ref", NULL);
+-	clk_add_alias("uart", NULL, "ref", NULL);
+ }
+ 
+ void __init ath79_clocks_init(void)
+ {
++	const char *wdt;
++	const char *uart;
++
+ 	if (soc_is_ar71xx())
+ 		ar71xx_clocks_init();
+ 	else if (soc_is_ar724x() || soc_is_ar913x())
+@@ -651,6 +633,20 @@ void __init ath79_clocks_init(void)
+ 		qca956x_clocks_init();
+ 	else
+ 		BUG();
++
++	if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) {
++		wdt = "ahb";
++		uart = "ahb";
++	} else if (soc_is_ar933x()) {
++		wdt = "ahb";
++		uart = "ref";
++	} else {
++		wdt = "ref";
++		uart = "ref";
++	}
++
++	clk_add_alias("wdt", NULL, wdt, NULL);
++	clk_add_alias("uart", NULL, uart, NULL);
+ }
+ 
+ unsigned long __init