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authorDaniel Golle <daniel@makrotopia.org>2019-06-12 01:14:25 +0200
committerDaniel Golle <daniel@makrotopia.org>2019-06-12 01:18:52 +0200
commit000d400baa0af2e42c9a462e42df7dc9abde1ec7 (patch)
treea11c2dd570e8f02c4a141f135fc8db1e1d391ef2 /target/linux/ath79/patches-4.19/0022-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch
parentc4e727f01cc40bd57274d0b885b0f75cde9c4683 (diff)
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kernel: drop everything not on kernel version 4.14
* Remove testing patches for kernel version 4.19 * remove targets ar7, ixp4xx, orion Those targets are still on kernel 4.9, patches for 4.14 were not ready in time. They may be readded once people prepare and test patches for kernel 4.14. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Diffstat (limited to 'target/linux/ath79/patches-4.19/0022-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch')
-rw-r--r--target/linux/ath79/patches-4.19/0022-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch114
1 files changed, 0 insertions, 114 deletions
diff --git a/target/linux/ath79/patches-4.19/0022-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch b/target/linux/ath79/patches-4.19/0022-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch
deleted file mode 100644
index 389edc45a8..0000000000
--- a/target/linux/ath79/patches-4.19/0022-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch
+++ /dev/null
@@ -1,114 +0,0 @@
-From 339c191a95e978353c9ba3aafab0261e14de109b Mon Sep 17 00:00:00 2001
-From: Felix Fietkau <nbd@nbd.name>
-Date: Tue, 6 Mar 2018 13:22:43 +0100
-Subject: [PATCH 22/33] MIPS: ath79: move legacy "wdt" and "uart" clock aliases
- out of soc init
-
-Preparation for reusing functions for DT
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
-Signed-off-by: John Crispin <john@phrozen.org>
----
- arch/mips/ath79/clock.c | 38 +++++++++++++++++---------------------
- 1 file changed, 17 insertions(+), 21 deletions(-)
-
---- a/arch/mips/ath79/clock.c
-+++ b/arch/mips/ath79/clock.c
-@@ -110,9 +110,6 @@ static void __init ar71xx_clocks_init(vo
- ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
--
-- clk_add_alias("wdt", NULL, "ahb", NULL);
-- clk_add_alias("uart", NULL, "ahb", NULL);
- }
-
- static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
-@@ -140,9 +137,6 @@ static void __init ar724x_clocks_init(vo
- ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
-
- ar724x_clk_init(ref_clk, ath79_pll_base);
--
-- clk_add_alias("wdt", NULL, "ahb", NULL);
-- clk_add_alias("uart", NULL, "ahb", NULL);
- }
-
- static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
-@@ -218,9 +212,6 @@ static void __init ar933x_clocks_init(vo
- ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
-
- ar9330_clk_init(ref_clk, ath79_pll_base);
--
-- clk_add_alias("wdt", NULL, "ahb", NULL);
-- clk_add_alias("uart", NULL, "ref", NULL);
- }
-
- static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
-@@ -353,9 +344,6 @@ static void __init ar934x_clocks_init(vo
- ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-
-- clk_add_alias("wdt", NULL, "ref", NULL);
-- clk_add_alias("uart", NULL, "ref", NULL);
--
- iounmap(dpll_base);
- }
-
-@@ -439,9 +427,6 @@ static void __init qca953x_clocks_init(v
- ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
--
-- clk_add_alias("wdt", NULL, "ref", NULL);
-- clk_add_alias("uart", NULL, "ref", NULL);
- }
-
- static void __init qca955x_clocks_init(void)
-@@ -524,9 +509,6 @@ static void __init qca955x_clocks_init(v
- ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
--
-- clk_add_alias("wdt", NULL, "ref", NULL);
-- clk_add_alias("uart", NULL, "ref", NULL);
- }
-
- static void __init qca956x_clocks_init(void)
-@@ -628,13 +610,13 @@ static void __init qca956x_clocks_init(v
- ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
- ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
- ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
--
-- clk_add_alias("wdt", NULL, "ref", NULL);
-- clk_add_alias("uart", NULL, "ref", NULL);
- }
-
- void __init ath79_clocks_init(void)
- {
-+ const char *wdt;
-+ const char *uart;
-+
- if (soc_is_ar71xx())
- ar71xx_clocks_init();
- else if (soc_is_ar724x() || soc_is_ar913x())
-@@ -651,6 +633,20 @@ void __init ath79_clocks_init(void)
- qca956x_clocks_init();
- else
- BUG();
-+
-+ if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) {
-+ wdt = "ahb";
-+ uart = "ahb";
-+ } else if (soc_is_ar933x()) {
-+ wdt = "ahb";
-+ uart = "ref";
-+ } else {
-+ wdt = "ref";
-+ uart = "ref";
-+ }
-+
-+ clk_add_alias("wdt", NULL, wdt, NULL);
-+ clk_add_alias("uart", NULL, uart, NULL);
- }
-
- unsigned long __init