ath79: add new OF only target for QCA MIPS silicon

This target aims to replace ar71xx mid-term. The big part that is still
missing is making the MMIO/AHB wifi work using OF. NAND and mikrotik
subtargets will follow.

Signed-off-by: John Crispin <john@phrozen.org>

1 files changed, 238 insertions, 0 deletions

diff --git a/target/linux/ath79/patches-4.14/0030-MIPS-ath79-pass-PLL-base-to-clock-init-functions.patch b/target/linux/ath79/patches-4.14/0030-MIPS-ath79-pass-PLL-base-to-clock-init-functions.patch
new file mode 100644
index 0000000000..d326880d84
--- /dev/null
+++ b/target/linux/ath79/patches-4.14/0030-MIPS-ath79-pass-PLL-base-to-clock-init-functions.patch
@@ -0,0 +1,238 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 6 Mar 2018 13:23:20 +0100
+Subject: [PATCH] MIPS: ath79: pass PLL base to clock init functions
+
+Preparation for passing the mapped base via DT
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -79,7 +79,7 @@ static struct clk * __init ath79_set_ff_
+ 	return clk;
+ }
+ 
+-static void __init ar71xx_clocks_init(void)
++static void __init ar71xx_clocks_init(void __iomem *pll_base)
+ {
+ 	unsigned long ref_rate;
+ 	unsigned long cpu_rate;
+@@ -91,7 +91,7 @@ static void __init ar71xx_clocks_init(vo
+ 
+ 	ref_rate = AR71XX_BASE_FREQ;
+ 
+-	pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
++	pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
+ 
+ 	div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
+ 	freq = div * ref_rate;
+@@ -129,13 +129,13 @@ static void __init ar724x_clk_init(struc
+ 	ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
+ }
+ 
+-static void __init ar724x_clocks_init(void)
++static void __init ar724x_clocks_init(void __iomem *pll_base)
+ {
+ 	struct clk *ref_clk;
+ 
+ 	ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
+ 
+-	ar724x_clk_init(ref_clk, ath79_pll_base);
++	ar724x_clk_init(ref_clk, pll_base);
+ }
+ 
+ static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
+@@ -196,7 +196,7 @@ static void __init ar9330_clk_init(struc
+ 			 ref_div * out_div * ahb_div);
+ }
+ 
+-static void __init ar933x_clocks_init(void)
++static void __init ar933x_clocks_init(void __iomem *pll_base)
+ {
+ 	struct clk *ref_clk;
+ 	unsigned long ref_rate;
+@@ -233,7 +233,7 @@ static u32 __init ar934x_get_pll_freq(u3
+ 	return ret;
+ }
+ 
+-static void __init ar934x_clocks_init(void)
++static void __init ar934x_clocks_init(void __iomem *pll_base)
+ {
+ 	unsigned long ref_rate;
+ 	unsigned long cpu_rate;
+@@ -264,7 +264,7 @@ static void __init ar934x_clocks_init(vo
+ 			  AR934X_SRIF_DPLL1_REFDIV_MASK;
+ 		frac = 1 << 18;
+ 	} else {
+-		pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
++		pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);
+ 		out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+ 			AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ 		ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+@@ -291,7 +291,7 @@ static void __init ar934x_clocks_init(vo
+ 			  AR934X_SRIF_DPLL1_REFDIV_MASK;
+ 		frac = 1 << 18;
+ 	} else {
+-		pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
++		pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);
+ 		out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
+ 			  AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
+ 		ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
+@@ -306,7 +306,7 @@ static void __init ar934x_clocks_init(vo
+ 	ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
+ 				      nfrac, frac, out_div);
+ 
+-	clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
++	clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
+ 
+ 	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
+ 		  AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
+@@ -346,7 +346,7 @@ static void __init ar934x_clocks_init(vo
+ 	iounmap(dpll_base);
+ }
+ 
+-static void __init qca953x_clocks_init(void)
++static void __init qca953x_clocks_init(void __iomem *pll_base)
+ {
+ 	unsigned long ref_rate;
+ 	unsigned long cpu_rate;
+@@ -362,7 +362,7 @@ static void __init qca953x_clocks_init(v
+ 	else
+ 		ref_rate = 25 * 1000 * 1000;
+ 
+-	pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
++	pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
+ 	out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+ 		  QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ 	ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+@@ -376,7 +376,7 @@ static void __init qca953x_clocks_init(v
+ 	cpu_pll += frac * (ref_rate >> 6) / ref_div;
+ 	cpu_pll /= (1 << out_div);
+ 
+-	pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
++	pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);
+ 	out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
+ 		  QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
+ 	ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
+@@ -390,7 +390,7 @@ static void __init qca953x_clocks_init(v
+ 	ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
+ 	ddr_pll /= (1 << out_div);
+ 
+-	clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
++	clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG);
+ 
+ 	postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
+ 		  QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
+@@ -428,7 +428,7 @@ static void __init qca953x_clocks_init(v
+ 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+ }
+ 
+-static void __init qca955x_clocks_init(void)
++static void __init qca955x_clocks_init(void __iomem *pll_base)
+ {
+ 	unsigned long ref_rate;
+ 	unsigned long cpu_rate;
+@@ -444,7 +444,7 @@ static void __init qca955x_clocks_init(v
+ 	else
+ 		ref_rate = 25 * 1000 * 1000;
+ 
+-	pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
++	pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
+ 	out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+ 		  QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ 	ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+@@ -458,7 +458,7 @@ static void __init qca955x_clocks_init(v
+ 	cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
+ 	cpu_pll /= (1 << out_div);
+ 
+-	pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
++	pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);
+ 	out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
+ 		  QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
+ 	ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
+@@ -472,7 +472,7 @@ static void __init qca955x_clocks_init(v
+ 	ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
+ 	ddr_pll /= (1 << out_div);
+ 
+-	clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
++	clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG);
+ 
+ 	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
+ 		  QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
+@@ -510,7 +510,7 @@ static void __init qca955x_clocks_init(v
+ 	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+ }
+ 
+-static void __init qca956x_clocks_init(void)
++static void __init qca956x_clocks_init(void __iomem *pll_base)
+ {
+ 	unsigned long ref_rate;
+ 	unsigned long cpu_rate;
+@@ -526,13 +526,13 @@ static void __init qca956x_clocks_init(v
+ 	else
+ 		ref_rate = 25 * 1000 * 1000;
+ 
+-	pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
++	pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
+ 	out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+ 		  QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ 	ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+ 		  QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
+ 
+-	pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
++	pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);
+ 	nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
+ 	       QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
+ 	hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
+@@ -545,12 +545,12 @@ static void __init qca956x_clocks_init(v
+ 	cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
+ 	cpu_pll /= (1 << out_div);
+ 
+-	pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
++	pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);
+ 	out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
+ 		  QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
+ 	ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
+ 		  QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
+-	pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
++	pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);
+ 	nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
+ 	       QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
+ 	hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
+@@ -563,7 +563,7 @@ static void __init qca956x_clocks_init(v
+ 	ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
+ 	ddr_pll /= (1 << out_div);
+ 
+-	clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
++	clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG);
+ 
+ 	postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
+ 		  QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
+@@ -607,19 +607,19 @@ void __init ath79_clocks_init(void)
+ 	const char *uart;
+ 
+ 	if (soc_is_ar71xx())
+-		ar71xx_clocks_init();
++		ar71xx_clocks_init(ath79_pll_base);
+ 	else if (soc_is_ar724x() || soc_is_ar913x())
+-		ar724x_clocks_init();
++		ar724x_clocks_init(ath79_pll_base);
+ 	else if (soc_is_ar933x())
+-		ar933x_clocks_init();
++		ar933x_clocks_init(ath79_pll_base);
+ 	else if (soc_is_ar934x())
+-		ar934x_clocks_init();
++		ar934x_clocks_init(ath79_pll_base);
+ 	else if (soc_is_qca953x())
+-		qca953x_clocks_init();
++		qca953x_clocks_init(ath79_pll_base);
+ 	else if (soc_is_qca955x())
+-		qca955x_clocks_init();
++		qca955x_clocks_init(ath79_pll_base);
+ 	else if (soc_is_qca956x() || soc_is_tp9343())
+-		qca956x_clocks_init();
++		qca956x_clocks_init(ath79_pll_base);
+ 	else
+ 		BUG();
+