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authorJohn Crispin <john@phrozen.org>2018-05-06 10:20:11 +0200
committerJohn Crispin <john@phrozen.org>2018-05-07 08:06:51 +0200
commit53c474abbdfef8eb3499e2d10c9ad491788b8a72 (patch)
treeacd19415420664f59bc63c1ceb4ad37bb7323027 /target/linux/ath79/patches-4.14/0029-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch
parent3dc523f232ff01d31d59345f5fa6de508d5059ef (diff)
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ath79: add new OF only target for QCA MIPS silicon
This target aims to replace ar71xx mid-term. The big part that is still missing is making the MMIO/AHB wifi work using OF. NAND and mikrotik subtargets will follow. Signed-off-by: John Crispin <john@phrozen.org>
Diffstat (limited to 'target/linux/ath79/patches-4.14/0029-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch')
-rw-r--r--target/linux/ath79/patches-4.14/0029-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch110
1 files changed, 110 insertions, 0 deletions
diff --git a/target/linux/ath79/patches-4.14/0029-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch b/target/linux/ath79/patches-4.14/0029-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch
new file mode 100644
index 0000000000..07e750a96c
--- /dev/null
+++ b/target/linux/ath79/patches-4.14/0029-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch
@@ -0,0 +1,110 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 6 Mar 2018 13:22:43 +0100
+Subject: [PATCH] MIPS: ath79: move legacy "wdt" and "uart" clock aliases
+ out of soc init
+
+Preparation for reusing functions for DT
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -109,9 +109,6 @@ static void __init ar71xx_clocks_init(vo
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+-
+- clk_add_alias("wdt", NULL, "ahb", NULL);
+- clk_add_alias("uart", NULL, "ahb", NULL);
+ }
+
+ static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
+@@ -139,9 +136,6 @@ static void __init ar724x_clocks_init(vo
+ ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
+
+ ar724x_clk_init(ref_clk, ath79_pll_base);
+-
+- clk_add_alias("wdt", NULL, "ahb", NULL);
+- clk_add_alias("uart", NULL, "ahb", NULL);
+ }
+
+ static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
+@@ -217,9 +211,6 @@ static void __init ar933x_clocks_init(vo
+ ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
+
+ ar9330_clk_init(ref_clk, ath79_pll_base);
+-
+- clk_add_alias("wdt", NULL, "ahb", NULL);
+- clk_add_alias("uart", NULL, "ref", NULL);
+ }
+
+ static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
+@@ -352,9 +343,6 @@ static void __init ar934x_clocks_init(vo
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+
+- clk_add_alias("wdt", NULL, "ref", NULL);
+- clk_add_alias("uart", NULL, "ref", NULL);
+-
+ iounmap(dpll_base);
+ }
+
+@@ -438,9 +426,6 @@ static void __init qca953x_clocks_init(v
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+-
+- clk_add_alias("wdt", NULL, "ref", NULL);
+- clk_add_alias("uart", NULL, "ref", NULL);
+ }
+
+ static void __init qca955x_clocks_init(void)
+@@ -523,9 +508,6 @@ static void __init qca955x_clocks_init(v
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+-
+- clk_add_alias("wdt", NULL, "ref", NULL);
+- clk_add_alias("uart", NULL, "ref", NULL);
+ }
+
+ static void __init qca956x_clocks_init(void)
+@@ -617,13 +599,13 @@ static void __init qca956x_clocks_init(v
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+-
+- clk_add_alias("wdt", NULL, "ref", NULL);
+- clk_add_alias("uart", NULL, "ref", NULL);
+ }
+
+ void __init ath79_clocks_init(void)
+ {
++ const char *wdt;
++ const char *uart;
++
+ if (soc_is_ar71xx())
+ ar71xx_clocks_init();
+ else if (soc_is_ar724x() || soc_is_ar913x())
+@@ -640,6 +622,20 @@ void __init ath79_clocks_init(void)
+ qca956x_clocks_init();
+ else
+ BUG();
++
++ if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) {
++ wdt = "ahb";
++ uart = "ahb";
++ } else if (soc_is_ar933x()) {
++ wdt = "ahb";
++ uart = "ref";
++ } else {
++ wdt = "ref";
++ uart = "ref";
++ }
++
++ clk_add_alias("wdt", NULL, wdt, NULL);
++ clk_add_alias("uart", NULL, uart, NULL);
+ }
+
+ unsigned long __init