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authorChuanhong Guo <gch981213@gmail.com>2018-08-21 19:39:16 +0800
committerJohn Crispin <john@phrozen.org>2018-08-28 11:26:53 +0200
commit028daa99743b87d33759529d40835cb51dced5cc (patch)
tree96c9894858af9d1296e7d5f630f61c99d0c67369 /target/linux/ath79/files/drivers
parent9300eda00fa91fda22cea56677db5dfa2371ddcb (diff)
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ath79: ag71xx: apply interface mode to MII0/1_CTRL on ar71xx/ar913x
We currently don't have any code configuring interface mode in ath79, meaning that we relies on bootloader to set the correct interface mode. This patch added code to set interface correctly so that everything works even if bootloader configures it wrong.(e.g. on WNDR3800 u-boot set the second GMAC mode to RMII but it should be RGMII.) Introduced "qca,mac-idx" for the difference in MII_CTRL register value. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Diffstat (limited to 'target/linux/ath79/files/drivers')
-rw-r--r--target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h2
-rw-r--r--target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c68
2 files changed, 70 insertions, 0 deletions
diff --git a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
index 377b9f8fe2..9aac1998a8 100644
--- a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
+++ b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
@@ -154,6 +154,8 @@ struct ag71xx {
struct ag71xx_ring rx_ring ____cacheline_aligned;
struct ag71xx_ring tx_ring ____cacheline_aligned;
+ int mac_idx;
+
u16 desc_pktlen_mask;
u16 rx_buf_size;
u8 rx_buf_offset;
diff --git a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
index 1e0bb6937f..d029197d4c 100644
--- a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
+++ b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
@@ -529,6 +529,60 @@ static void ath79_set_pll(struct ag71xx *ag)
udelay(100);
}
+static void ath79_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if)
+{
+ u32 t;
+
+ t = __raw_readl(ag->mii_base);
+ t &= ~(AR71XX_MII_CTRL_IF_MASK);
+ t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
+ __raw_writel(t, ag->mii_base);
+}
+
+static void ath79_mii0_ctrl_set_if(struct ag71xx *ag)
+{
+ unsigned int mii_if;
+
+ switch (ag->phy_if_mode) {
+ case PHY_INTERFACE_MODE_MII:
+ mii_if = AR71XX_MII0_CTRL_IF_MII;
+ break;
+ case PHY_INTERFACE_MODE_GMII:
+ mii_if = AR71XX_MII0_CTRL_IF_GMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ mii_if = AR71XX_MII0_CTRL_IF_RGMII;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ mii_if = AR71XX_MII0_CTRL_IF_RMII;
+ break;
+ default:
+ WARN(1, "Impossible PHY mode defined.\n");
+ return;
+ }
+
+ ath79_mii_ctrl_set_if(ag, mii_if);
+}
+
+static void ath79_mii1_ctrl_set_if(struct ag71xx *ag)
+{
+ unsigned int mii_if;
+
+ switch (ag->phy_if_mode) {
+ case PHY_INTERFACE_MODE_RMII:
+ mii_if = AR71XX_MII1_CTRL_IF_RMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ mii_if = AR71XX_MII1_CTRL_IF_RGMII;
+ break;
+ default:
+ WARN(1, "Impossible PHY mode defined.\n");
+ return;
+ }
+
+ ath79_mii_ctrl_set_if(ag, mii_if);
+}
+
static void ath79_mii_ctrl_set_speed(struct ag71xx *ag)
{
unsigned int mii_speed;
@@ -1427,6 +1481,20 @@ static int ag71xx_probe(struct platform_device *pdev)
goto err_free;
}
+ if (of_property_read_u32(np, "qca,mac-idx", &ag->mac_idx))
+ ag->mac_idx = -1;
+ if (ag->mii_base)
+ switch (ag->mac_idx) {
+ case 0:
+ ath79_mii0_ctrl_set_if(ag);
+ break;
+ case 1:
+ ath79_mii1_ctrl_set_if(ag);
+ break;
+ default:
+ break;
+ }
+
netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);