ath79: add support for D-Link DIR-842 C1

Hardware spec of DIR-842 C1:
SoC: QCA9563
DRAM: 128MB DDR2
Flash: 16MB SPI-NOR
Switch: QCA8337N
WiFi 5.8GHz: QCA9888
WiFi 2.4Ghz: QCA9563
USB: circuit onboard, but components are not soldered

Flash instructions:

1. Upgrade the factory.bin through the factory web interface or
   the u-boot failsafe interface.
   The firmware will boot up correctly for the first time.
   Do not power off the device after OpenWrt has booted.
   Otherwise the u-boot will enter failsafe mode as the checksum
   of the firmware has been changed.
2. Upgrade the sysupgrade.bin in OpenWrt.
   After upgrading completes the u-boot won't complain about the
   firmware checksum and it's OK to use now.
3. If you powered off the device before upgrading the sysupgrade.bin,
   just upgrade the factory.bin through the u-boot failsafe interface
   and then goto step 2.

Signed-off-by: Jackson Lim <jackcolentern@gmail.com>
[fix whitespace issues]
Signed-off-by: David Bauer <mail@david-bauer.net>

3 files changed, 188 insertions, 141 deletions

diff --git a/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi b/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi
new file mode 100644
index 0000000000..ac8fe3ae0a
--- /dev/null
+++ b/target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "qca956x.dtsi"
+
+/ {
+	chosen {
+		bootargs = "console=ttyS0,115200n8";
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		wps {
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+			debounce-interval = <60>;
+		};
+
+		reset {
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+			debounce-interval = <60>;
+		};
+	};
+
+	// Pull up on boot - otherwise the reset button won't work
+	reset-button {
+		gpio-hog;
+		output-high;
+		gpios = <11 GPIO_ACTIVE_LOW>;
+		line-name = "reset-button";
+	};
+};
+
+&uart {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&spi {
+	status = "okay";
+	num-cs = <1>;
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <30000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x000000 0x40000>;
+				read-only;
+			};
+
+			partition@40000 {
+				label = "u-boot-env";
+				reg = <0x040000 0x10000>;
+				read-only;
+			};
+
+			partition@50000 {
+				label = "devdata";
+				reg = <0x050000 0x10000>;
+				read-only;
+			};
+
+			partition@60000 {
+				label = "devconf";
+				reg = <0x060000 0x10000>;
+				read-only;
+			};
+
+			partition@70000 {
+				label = "misc";
+				reg = <0x070000 0x10000>;
+				read-only;
+			};
+
+			partition@80000 {
+				compatible = "seama";
+				label = "firmware";
+				reg = <0x080000 0xf50000>;
+			};
+
+			art: partition@fd0000 {
+				label = "art";
+				reg = <0xfd0000 0x010000>;
+				read-only;
+			};
+
+			partition@fe0000 {
+				label = "reserved";
+				reg = <0xfe0000 0x20000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&mdio0 {
+	status = "okay";
+
+	phy-mask = <0>;
+
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+		qca,mib-poll-interval = <500>;
+
+		qca,ar8327-initvals = <
+			0x04 0x00080080 /* PORT0 PAD MODE CTRL */
+			0x10 0x81000080 /* POWER_ON_STRIP */
+			0x50 0xcc35cc35 /* LED_CTRL0 */
+			0x54 0xcb37cb37 /* LED_CTRL1 */
+			0x58 0x00000000 /* LED_CTRL2 */
+			0x5c 0x00f3cf00 /* LED_CTRL3 */
+			0x7c 0x0000007e /* PORT0_STATUS */
+			>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+
+	pll-data = <0x03000101 0x00000101 0x00001919>;
+
+	phy-mode = "sgmii";
+	phy-handle = <&phy0>;
+};
+
+&wmac {
+	status = "okay";
+	qca,no-eeprom;
+};
diff --git a/target/linux/ath79/dts/qca9563_dlink_dir-842-c1.dts b/target/linux/ath79/dts/qca9563_dlink_dir-842-c1.dts
new file mode 100644
index 0000000000..971c567924
--- /dev/null
+++ b/target/linux/ath79/dts/qca9563_dlink_dir-842-c1.dts
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include "qca9563_dlink_dir-842-c.dtsi"
+
+/ {
+	compatible = "dlink,dir-842-c1", "qca,qca9563";
+	model = "D-Link DIR-842 C1";
+
+	aliases {
+		led-boot = &power;
+		led-failsafe = &power;
+		led-running = &power;
+		led-upgrade = &power;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		wps {
+			label = "dir-842-c1:green:wps";
+			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
+		};
+
+		power: power {
+			label = "dir-842-c1:green:power";
+			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+		};
+
+		internet {
+			label = "dir-842-c1:green:internet";
+			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
+		};
+
+		wlan {
+			label = "dir-842-c1:green:wlan";
+			gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy0tpt";
+		};
+	};
+};
diff --git a/target/linux/ath79/dts/qca9563_dlink_dir-842-c2.dts b/target/linux/ath79/dts/qca9563_dlink_dir-842-c2.dts
index 49e3855268..9d70dd9be7 100644
--- a/target/linux/ath79/dts/qca9563_dlink_dir-842-c2.dts
+++ b/target/linux/ath79/dts/qca9563_dlink_dir-842-c2.dts
@@ -1,14 +1,11 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-#include "qca956x.dtsi"
+#include "qca9563_dlink_dir-842-c.dtsi"
 
 / {
-	model = "D-Link DIR-842 C2";
 	compatible = "dlink,dir-842-c2", "qca,qca9563";
+	model = "D-Link DIR-842 C2";
 
 	aliases {
 		led-boot = &power;
@@ -17,10 +14,6 @@
 		led-upgrade = &power;
 	};
 
-	chosen {
-		bootargs = "console=ttyS0,115200n8";
-	};
-
 	leds {
 		compatible = "gpio-leds";
 
@@ -45,138 +38,6 @@
 			linux,default-trigger = "phy0tpt";
 		};
 	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		wps {
-			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
-			debounce-interval = <60>;
-		};
-
-		reset {
-			linux,code = <KEY_RESTART>;
-			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
-			debounce-interval = <60>;
-		};
-	};
-
-	// Pull up on boot - otherwise the reset button won't work
-	reset-button {
-		gpio-hog;
-		output-high;
-		gpios = <11 GPIO_ACTIVE_LOW>;
-		line-name = "reset-button";
-	};
-};
-
-&uart {
-	status = "okay";
-};
-
-&pcie {
-	status = "okay";
-};
-
-&spi {
-	status = "okay";
-	num-cs = <1>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <30000000>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "u-boot";
-				reg = <0x000000 0x40000>;
-				read-only;
-			};
-
-			partition@40000 {
-				label = "u-boot-env";
-				reg = <0x040000 0x10000>;
-				read-only;
-			};
-
-			partition@50000 {
-				label = "devdata";
-				reg = <0x050000 0x10000>;
-				read-only;
-			};
-
-			partition@60000 {
-				label = "devconf";
-				reg = <0x060000 0x10000>;
-				read-only;
-			};
-
-			partition@70000 {
-				label = "misc";
-				reg = <0x070000 0x10000>;
-				read-only;
-			};
-
-			partition@80000 {
-				compatible = "seama";
-				label = "firmware";
-				reg = <0x080000 0xf50000>;
-			};
-
-			art: partition@fd0000 {
-				label = "art";
-				reg = <0xfd0000 0x010000>;
-				read-only;
-			};
-
-			partition@fe0000 {
-				label = "reserved";
-				reg = <0xfe0000 0x20000>;
-				read-only;
-			};
-		};
-	};
-};
-
-&mdio0 {
-	status = "okay";
-
-	phy-mask = <0>;
-
-	phy0: ethernet-phy@0 {
-		reg = <0>;
-		qca,mib-poll-interval = <500>;
-
-		qca,ar8327-initvals = <
-			0x04 0x00080080 /* PORT0 PAD MODE CTRL */
-			0x10 0x81000080 /* POWER_ON_STRIP */
-			0x50 0xcc35cc35 /* LED_CTRL0 */
-			0x54 0xcb37cb37 /* LED_CTRL1 */
-			0x58 0x00000000 /* LED_CTRL2 */
-			0x5c 0x00f3cf00 /* LED_CTRL3 */
-			0x7c 0x0000007e /* PORT0_STATUS */
-			>;
-	};
-};
-
-&eth0 {
-	status = "okay";
-
-	pll-data = <0x03000101 0x00000101 0x00001919>;
-
-	phy-mode = "sgmii";
-	phy-handle = <&phy0>;
-};
-
-&wmac {
-	status = "okay";
-	qca,no-eeprom;
 };
 
 &usb_phy0 {