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authorChuanhong Guo <gch981213@gmail.com>2018-08-13 20:32:02 +0800
committerMathias Kresin <dev@kresin.me>2018-08-14 10:19:37 +0200
commit1213504750bf27b46fd958d236fcf56f33d2d8cd (patch)
tree6b682a3fbb8bdbb1b8dd4f86fcaa2ba57cf545c0 /target/linux/ath79/dts
parent8db6522531531348952b161fd4de46a7eca481d6 (diff)
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ath79: add support for TP-Link TL-WR941N/ND v2/v3
Specification: - SoC: Atheros AR9132 - Flash: 4 MB - RAM: 32 MB - Ethernet: Marvell 88E6060 with 5 FE ports. Flash instruction: Upload the generated factory firmware on web interface. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Diffstat (limited to 'target/linux/ath79/dts')
-rw-r--r--target/linux/ath79/dts/ar9132_tplink_tl-wr941-v2.dts164
1 files changed, 164 insertions, 0 deletions
diff --git a/target/linux/ath79/dts/ar9132_tplink_tl-wr941-v2.dts b/target/linux/ath79/dts/ar9132_tplink_tl-wr941-v2.dts
new file mode 100644
index 0000000000..9928a80f52
--- /dev/null
+++ b/target/linux/ath79/dts/ar9132_tplink_tl-wr941-v2.dts
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9132.dtsi"
+
+/ {
+ compatible = "tplink,tl-wr941-v2", "qca,ar9132";
+ model = "TP-Link TL-WR941N/ND v2/v3";
+
+ aliases {
+ led-status = &led_system;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ button0 {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
+ debounce-interval = <60>;
+ };
+
+ button1 {
+ label = "qss";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
+ debounce-interval = <60>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_system: system {
+ label = "tp-link:green:system";
+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+ };
+
+ qss_r {
+ label = "tp-link:red:qss";
+ gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
+ };
+
+ qss_g {
+ label = "tp-link:green:qss";
+ gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ wlan {
+ label = "tp-link:green:wlan";
+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ linux,default-trigger = "phy0tpt";
+ };
+ };
+
+ dsa {
+ compatible = "marvell,dsa";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsa,mii-bus = <&mdio0>;
+ dsa,ethernet = <&eth0>;
+
+ switch@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "wan";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan3";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan4";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ };
+ };
+ };
+};
+
+&uart {
+ status = "okay";
+};
+
+&spi {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uboot: partition@0 {
+ label = "u-boot";
+ reg = <0x000000 0x20000>;
+ read-only;
+ };
+
+ partition@20000 {
+ label = "firmware";
+ reg = <0x020000 0x3d0000>;
+ };
+
+ art: partition@3f0000 {
+ label = "art";
+ reg = <0x3f0000 0x10000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&mdio0 {
+ status = "okay";
+};
+
+&eth0 {
+ status = "okay";
+
+ phy-mode = "rmii";
+ mtd-mac-address = <&uboot 0x1fc00>;
+
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+};
+
+&wmac {
+ status = "okay";
+ mtd-cal-data = <&art 0x1000>;
+ mtd-mac-address = <&uboot 0x1fc00>;
+};