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author | Thibaut VARÈNE <hacks@slashdirt.org> | 2022-04-14 12:39:05 +0200 |
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committer | Petr Štetiar <ynezz@true.cz> | 2022-04-15 08:14:50 +0200 |
commit | 321ec22f5246aeb20f57e88ecc149a272f469bd3 (patch) | |
tree | 7e45d6966331170a3bfcc852612bf9d38cbdc4e5 /target/linux/ath79/dts/qca9533_yuncore_a930.dts | |
parent | 708b883168e624ede9f5897a55e5e722c6881d76 (diff) | |
download | upstream-321ec22f5246aeb20f57e88ecc149a272f469bd3.tar.gz upstream-321ec22f5246aeb20f57e88ecc149a272f469bd3.tar.bz2 upstream-321ec22f5246aeb20f57e88ecc149a272f469bd3.zip |
ath79: add support for Yuncore A930
Specification:
- QCA9533 (650 MHz), 64 or 128MB RAM, 16MB SPI NOR
- 2x 10/100 Mbps Ethernet, with 802.3at PoE support (WAN)
- 2T2R 802.11b/g/n 2.4GHz
Flash instructions:
If your device comes with generic QSDK based firmware, you can login
over telnet (login: root, empty password, default IP: 192.168.188.253),
issue first (important!) 'fw_setenv' command and then perform regular
upgrade, using 'sysupgrade -n -F ...' (you can use 'wget' to download
image to the device, SSH server is not available):
fw_setenv bootcmd "bootm 0x9f050000 || bootm 0x9fe80000"
sysupgrade -n -F openwrt-...-yuncore_...-squashfs-sysupgrade.bin
In case your device runs firmware with YunCore custom GUI, you can use
U-Boot recovery mode:
1. Set a static IP 192.168.0.141/24 on PC and start TFTP server with
'tftp' image renamed to 'upgrade.bin'
2. Power the device with reset button pressed and release it after 5-7
seconds, recovery mode should start downloading image from server
(unfortunately, there is no visible indication that recovery got
enabled - in case of problems check TFTP server logs)
Signed-off-by: Clemens Hopfer <openwrt@wireloss.net>
Signed-off-by: Thibaut VARÈNE <hacks@slashdirt.org>
(cherry picked from commit a05dcb07241aa83a4416b56201e31b4af8518981)
Diffstat (limited to 'target/linux/ath79/dts/qca9533_yuncore_a930.dts')
-rw-r--r-- | target/linux/ath79/dts/qca9533_yuncore_a930.dts | 118 |
1 files changed, 118 insertions, 0 deletions
diff --git a/target/linux/ath79/dts/qca9533_yuncore_a930.dts b/target/linux/ath79/dts/qca9533_yuncore_a930.dts new file mode 100644 index 0000000000..089eebaa9c --- /dev/null +++ b/target/linux/ath79/dts/qca9533_yuncore_a930.dts @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qca953x.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + compatible = "yuncore,a930", "qca,qca9533"; + model = "YunCore A930"; + + aliases { + label-mac-device = ð1; + led-boot = &led_system; + led-failsafe = &led_system; + led-running = &led_system; + led-upgrade = &led_system; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_system: system { + label = "green:system"; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + wlan2g { + label = "blue:wlan2g"; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + }; +}; + +&spi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x000000 0x040000>; + read-only; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x040000 0x010000>; + }; + + partition@50000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x050000 0xfa0000>; + }; + + art: partition@ff0000 { + label = "art"; + reg = <0xff0000 0x010000>; + read-only; + }; + }; + }; +}; + +ð0 { + status = "okay"; + + phy-handle = <&swphy4>; + + nvmem-cells = <&macaddr_art_0>; + nvmem-cell-names = "mac-address"; +}; + +ð1 { + nvmem-cells = <&macaddr_art_6>; + nvmem-cell-names = "mac-address"; +}; + +&wmac { + status = "okay"; + mtd-cal-data = <&art 0x1000>; +}; + +&art { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; +}; |