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authorKristian Evensen <kristian.evensen@gmail.com>2019-05-31 15:43:14 +0200
committerPetr Štetiar <ynezz@true.cz>2019-06-05 10:24:36 +0200
commit046263095e007ba80bdf3525de32d7cce11734e8 (patch)
treee8bb1f8ba9910810e2fe2d327a7f99a3c9fe22da /target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts
parentc3a85189181827c8d5c2ab736428be30e4c13128 (diff)
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ath79: Add support for ZBT-WD323
ZBT-WD323 is a dual-LTE router based on AR9344. The detailed specifications are: * AR9344 560MHz/450MHz/225MHz (CPU/DDR/AHN). * 128 MB RAM * 16MB of flash(SPI-NOR, 22MHz) * 1x 2.4GHz wifi (Atheros AR9340) * 3x 10/100Mbos Ethernet (AR8229) * 1x USB2.0 port * 2x miniPCIe-slots (USB2.0 only) * 2x SIM slots (standard size) * 4x LEDs (1 gpio controlled) * 1x reset button * 1x 10 pin terminal block (RS232, RS485, 4x GPIO) * 2x CP210x UART bridge controllers (used for RS232 and RS485) * 1x 2 pin 5mm industrial interface (input voltage 12V~36V) * 1x DC jack * 1x RTC (PCF8563) Tested: - Ethernet switch - Wifi - USB port - MiniPCIe-slots (+ SIM slots) - Sysupgrade - Reset button - RS232 Intallation and recovery: The board ships with OpenWRT, but sysupgrade does not work as a different firmware format than what is expected is generated. The easiest way to install (and recover) the router, is to use the web-interface provided by the bootloader (Breed). While the interface is in Chinese, it is easy to use. First, in order to access the interface, you need to hold down the reset button for around five seconds. Then, go to 192.168.1.1 in your browser. Click on the second item in the list on the left to access the recovery page. The second item on the next page is where you select the firmware. Select the menu item containing "Atheros SDK" and "16MB" in the dropdown close to the buttom, and click on the button at the bottom to start installation/recovery. Notes: * RS232 is available on /dev/ttyUSB0 and RS485 on /dev/ttyUSB1 Signed-off-by: Kristian Evensen <kristian.evensen@gmail.com> [removed unused poll-interval from gpio-keys, i2c-gpio 4.19 compat] Signed-off-by: Petr Štetiar <ynezz@true.cz>
Diffstat (limited to 'target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts')
-rw-r--r--target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts166
1 files changed, 166 insertions, 0 deletions
diff --git a/target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts b/target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts
new file mode 100644
index 0000000000..d899cff9ef
--- /dev/null
+++ b/target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9344.dtsi"
+
+/ {
+ model = "ZBT WD323";
+ compatible = "zbtlink,zbt-wd323", "qca,ar9344";
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ i2c {
+ compatible = "i2c-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&enable_gpio15 &enable_gpio19>;
+
+ sda-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
+ scl-gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+
+ /* can be removed on 4.19 */
+ gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
+ <&gpio 15 GPIO_ACTIVE_LOW>;
+
+ pcf8563: pcf8563@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&enable_gpio20_gpio22>;
+
+ wifi {
+ label = "zbt-wd323:green:wifi";
+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "phy0tpt";
+ };
+
+ lan1 {
+ label = "zbt-wd323:orange:lan1";
+ gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
+ };
+
+ lan2 {
+ label = "zbt-wd323:orange:lan2";
+ gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
+ };
+
+ };
+};
+
+&wdt {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&enable_gpio21>;
+};
+
+&uart {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&jtag_disable_pins>;
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb_phy {
+ status = "okay";
+};
+
+&eth0 {
+ status = "okay";
+ phy-handle = <&swphy4>;
+ mtd-mac-address = <&art 0x0>;
+};
+
+&eth1 {
+ status = "okay";
+ mtd-mac-address = <&art 0x6>;
+};
+
+&spi {
+ num-chipselects = <1>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <22000000>;
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uboot@0 {
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+
+ uboot-env@40000 {
+ reg = <0x40000 0x10000>;
+ read-only;
+ };
+
+ firmware@50000 {
+ compatible = "denx,uimage";
+ reg = <0x50000 0xfa0000>;
+ };
+
+ art: art@ff0000 {
+ reg = <0xff0000 0x10000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&wmac {
+ status = "okay";
+ mtd-cal-data = <&art 0x1000>;
+ mtd-mac-address = <&art 0x1002>;
+};
+
+&pinmux {
+ enable_gpio15: pinmux_enable_gpio15 {
+ pinctrl-single,bits = <0xc 0x0 0xff000000>;
+ };
+
+ enable_gpio19: pinmux_enable_gpio19 {
+ pinctrl-single,bits = <0x10 0x0 0xff000000>;
+ };
+
+ enable_gpio20_gpio22: pinmux_enable_gpio20_gpio22 {
+ pinctrl-single,bits = <0x14 0x0 0xff00ff>;
+ };
+
+ enable_gpio21: pinmux_enable_gpio21 {
+ pinctrl-single,bits = <0x14 0x0 0xff00>;
+ };
+};