ath79: add new OF only target for QCA MIPS silicon

This target aims to replace ar71xx mid-term. The big part that is still
missing is making the MMIO/AHB wifi work using OF. NAND and mikrotik
subtargets will follow.

Signed-off-by: John Crispin <john@phrozen.org>

1 files changed, 160 insertions, 0 deletions

diff --git a/target/linux/ath79/dts/ar9330.dtsi b/target/linux/ath79/dts/ar9330.dtsi
new file mode 100644
index 0000000000..1c03cd8880
--- /dev/null
+++ b/target/linux/ath79/dts/ar9330.dtsi
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/ath79-clk.h>
+#include "ath79.dtsi"
+
+/ {
+	compatible = "qca,ar9330";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "mips,mips24Kc";
+			clocks = <&pll ATH79_CLK_CPU>;
+			reg = <0>;
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyATH0,115200";
+	};
+
+	ahb {
+		apb {
+			ddr_ctrl: memory-controller@18000000 {
+				compatible = "qca,ar7240-ddr-controller";
+				reg = <0x18000000 0x100>;
+
+				#qca,ddr-wb-channel-cells = <1>;
+			};
+
+			uart: uart@18020000 {
+				compatible = "qca,ar9330-uart";
+				reg = <0x18020000 0x14>;
+
+				interrupts = <3>;
+
+				clocks = <&pll ATH79_CLK_REF>;
+				clock-names = "uart";
+
+				status = "disabled";
+			};
+
+			gpio: gpio@18040000 {
+				compatible = "qca,ar7100-gpio";
+				reg = <0x18040000 0x34>;
+				interrupts = <2>;
+
+				ngpios = <30>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				status = "disabled";
+			};
+
+			pll: pll-controller@18050000 {
+				compatible = "qca,ar9330-pll";
+				reg = <0x18050000 0x100>;
+
+				#clock-cells = <1>;
+			};
+
+			rst: reset-controller@1806001c {
+				compatible = "qca,ar7100-reset";
+				reg = <0x1806001c 0x4>;
+
+				#reset-cells = <1>;
+			};
+		};
+
+		usb: usb@1b000100 {
+			compatible = "chipidea,usb2";
+			reg = <0x1b000000 0x200>;
+
+			interrupts = <3>;
+			resets = <&rst 5>;
+			reset-names = "usb-host";
+
+			phy-names = "usb-phy";
+			phys = <&usb_phy>;
+
+			status = "disabled";
+		};
+
+		spi: spi@1f000000 {
+			compatible = "qca,ar7100-spi";
+			reg = <0x1f000000 0x10>;
+
+			clocks = <&pll ATH79_CLK_AHB>;
+			clock-names = "ahb";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+		};
+
+		gmac: gmac@18070000 {
+			compatible = "qca,qr9330-gmac";
+			reg = <0x18070000 0x4>;
+		};
+	};
+
+	usb_phy: usb-phy {
+		compatible = "qca,ar7200-usb-phy";
+
+		reset-names = "usb-phy", "usb-suspend-override";
+		resets = <&rst 4>, <&rst 3>;
+
+		#phy-cells = <0>;
+
+		status = "disabled";
+	};
+};
+
+&cpuintc {
+	qca,ddr-wb-channel-interrupts = <2>, <3>;
+	qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>;
+};
+
+&eth0 {
+	compatible = "qca,ar9330-eth", "syscon";
+
+	pll-data = <0x00110000 0x00001099 0x00991099>;
+
+	resets = <&rst 9>;
+	reset-names = "mac";
+};
+
+&mdio0 {
+	regmap = <&eth1>;
+	builtin-switch;
+	resets = <&rst 23>;
+	reset-names = "mdio";
+};
+
+&mdio1 {
+	resets = <&rst 23>;
+	reset-names = "mdio";
+
+	builtin-switch;
+};
+
+&eth1 {
+	compatible = "qca,ar9330-eth", "syscon";
+
+	pll-data = <0x00110000 0x00001099 0x00991099>;
+	phy-mode = "gmii";
+
+	resets = <&rst 13>;
+	reset-names = "mac";
+};