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author | Chuanhong Guo <gch981213@gmail.com> | 2018-08-07 12:02:07 +0800 |
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committer | Mathias Kresin <dev@kresin.me> | 2018-08-09 18:44:57 +0200 |
commit | 387736af41444945da6a5e51748e91011569c03e (patch) | |
tree | b4e09e1c1aef9b377510f7812de0c56cf7a70c71 /target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts | |
parent | 23519edbcaa9cfd24b5a6fff44770f0fa9e13f3c (diff) | |
download | upstream-387736af41444945da6a5e51748e91011569c03e.tar.gz upstream-387736af41444945da6a5e51748e91011569c03e.tar.bz2 upstream-387736af41444945da6a5e51748e91011569c03e.zip |
ath79: ag71xx: remove PHY reset
Bit 8/12 of reset controller which is marked as PHY_RESET/SWITCH_RESET
in datasheets will trigger either a reset for builtin switch or assert
an external ETH0_RESET_L/ETH1_RESET_L pin, which are usually connected
to external PHY/switch. None of them should be triggered every time an
interface is brought up in ethernet driver.
Remove PHY reset support from ag71xx and definition for them in dtsi.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Diffstat (limited to 'target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts')
-rw-r--r-- | target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts b/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts index 58fc8a5832..b97b57f586 100644 --- a/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts +++ b/target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts @@ -140,9 +140,6 @@ phy-mode = "rgmii"; mtd-mac-address = <&uboot 0x1fc00>; - resets = <&rst 9>; - reset-names = "mac"; - fixed-link { speed = <1000>; full-duplex; |