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author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2022-09-15 17:09:28 +0300 |
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committer | Hauke Mehrtens <hauke@hauke-m.de> | 2022-10-22 00:51:25 +0200 |
commit | eb758a8fec2cee24e528008052fa2bd58482ca3a (patch) | |
tree | c4ea2a0e7246cc62314258cf6b1b8a5ad80f8df0 /target/linux/at91/patches-5.15/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch | |
parent | c5c37886cff1705ba9be9b33df3ab121bd27fe6b (diff) | |
download | upstream-eb758a8fec2cee24e528008052fa2bd58482ca3a.tar.gz upstream-eb758a8fec2cee24e528008052fa2bd58482ca3a.tar.bz2 upstream-eb758a8fec2cee24e528008052fa2bd58482ca3a.zip |
at91: kernel v5.15: copy config and patches from 5.10
Copy kernel config and patches from 5.10. Along with it
individual targets' config-default from 5.10 has been moved to
config-5.10.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Diffstat (limited to 'target/linux/at91/patches-5.15/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch')
-rw-r--r-- | target/linux/at91/patches-5.15/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch | 145 |
1 files changed, 145 insertions, 0 deletions
diff --git a/target/linux/at91/patches-5.15/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch b/target/linux/at91/patches-5.15/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch new file mode 100644 index 0000000000..247c901558 --- /dev/null +++ b/target/linux/at91/patches-5.15/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch @@ -0,0 +1,145 @@ +From fa9e6cd8f3ba4a277c06e4c1fb01cd69b3a57234 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev <eugen.hristev@microchip.com> +Date: Tue, 13 Apr 2021 12:57:25 +0200 +Subject: [PATCH 183/247] media: atmel: atmel-isc-base: add support for more + formats and additional pipeline modules + +Add support for additional formats supported by newer pipelines, and for +additional pipeline modules. + +Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> +Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> +Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> +--- + drivers/media/platform/atmel/atmel-isc-base.c | 48 +++++++++++++++---- + 1 file changed, 38 insertions(+), 10 deletions(-) + +--- a/drivers/media/platform/atmel/atmel-isc-base.c ++++ b/drivers/media/platform/atmel/atmel-isc-base.c +@@ -855,6 +855,8 @@ static int isc_try_validate_formats(stru + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_YUV422P: + case V4L2_PIX_FMT_YUYV: ++ case V4L2_PIX_FMT_UYVY: ++ case V4L2_PIX_FMT_VYUY: + ret = 0; + yuv = true; + break; +@@ -869,6 +871,7 @@ static int isc_try_validate_formats(stru + break; + case V4L2_PIX_FMT_GREY: + case V4L2_PIX_FMT_Y10: ++ case V4L2_PIX_FMT_Y16: + ret = 0; + grey = true; + break; +@@ -899,6 +902,8 @@ static int isc_try_validate_formats(stru + */ + static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump) + { ++ isc->try_config.rlp_cfg_mode = 0; ++ + switch (isc->try_config.fourcc) { + case V4L2_PIX_FMT_SBGGR8: + case V4L2_PIX_FMT_SGBRG8: +@@ -965,7 +970,19 @@ static int isc_try_configure_rlp_dma(str + isc->try_config.bpp = 16; + break; + case V4L2_PIX_FMT_YUYV: +- isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC; ++ isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV; ++ isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; ++ isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; ++ isc->try_config.bpp = 16; ++ break; ++ case V4L2_PIX_FMT_UYVY: ++ isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY; ++ isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; ++ isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; ++ isc->try_config.bpp = 16; ++ break; ++ case V4L2_PIX_FMT_VYUY: ++ isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 16; +@@ -976,8 +993,11 @@ static int isc_try_configure_rlp_dma(str + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 8; + break; ++ case V4L2_PIX_FMT_Y16: ++ isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH; ++ fallthrough; + case V4L2_PIX_FMT_Y10: +- isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10; ++ isc->try_config.rlp_cfg_mode |= ISC_RLP_CFG_MODE_DATY10; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 16; +@@ -1011,7 +1031,8 @@ static int isc_try_configure_pipeline(st + /* if sensor format is RAW, we convert inside ISC */ + if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { + isc->try_config.bits_pipeline = CFA_ENABLE | +- WB_ENABLE | GAM_ENABLES; ++ WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE | ++ CC_ENABLE; + } else { + isc->try_config.bits_pipeline = 0x0; + } +@@ -1020,8 +1041,9 @@ static int isc_try_configure_pipeline(st + /* if sensor format is RAW, we convert inside ISC */ + if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { + isc->try_config.bits_pipeline = CFA_ENABLE | +- CSC_ENABLE | WB_ENABLE | GAM_ENABLES | +- SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE; ++ CSC_ENABLE | GAM_ENABLES | WB_ENABLE | ++ SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE | ++ DPC_BLCENABLE; + } else { + isc->try_config.bits_pipeline = 0x0; + } +@@ -1031,33 +1053,39 @@ static int isc_try_configure_pipeline(st + if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { + isc->try_config.bits_pipeline = CFA_ENABLE | + CSC_ENABLE | WB_ENABLE | GAM_ENABLES | +- SUB422_ENABLE | CBC_ENABLE; ++ SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; + } else { + isc->try_config.bits_pipeline = 0x0; + } + break; + case V4L2_PIX_FMT_YUYV: ++ case V4L2_PIX_FMT_UYVY: ++ case V4L2_PIX_FMT_VYUY: + /* if sensor format is RAW, we convert inside ISC */ + if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { + isc->try_config.bits_pipeline = CFA_ENABLE | + CSC_ENABLE | WB_ENABLE | GAM_ENABLES | +- SUB422_ENABLE | CBC_ENABLE; ++ SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; + } else { + isc->try_config.bits_pipeline = 0x0; + } + break; + case V4L2_PIX_FMT_GREY: +- if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { ++ case V4L2_PIX_FMT_Y16: + /* if sensor format is RAW, we convert inside ISC */ ++ if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { + isc->try_config.bits_pipeline = CFA_ENABLE | + CSC_ENABLE | WB_ENABLE | GAM_ENABLES | +- CBC_ENABLE; ++ CBC_ENABLE | DPC_BLCENABLE; + } else { + isc->try_config.bits_pipeline = 0x0; + } + break; + default: +- isc->try_config.bits_pipeline = 0x0; ++ if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) ++ isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE; ++ else ++ isc->try_config.bits_pipeline = 0x0; + } + + /* Tune the pipeline to product specific */ |