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author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2022-02-04 15:57:50 +0200 |
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committer | Petr Štetiar <ynezz@true.cz> | 2022-02-24 19:05:28 +0100 |
commit | e58cd453d58b20c6a6f34d3591640aa19aa14d25 (patch) | |
tree | a4fef5f5d79575a7a60b516482ee114c1dbc932e /target/linux/at91/patches-5.10/245-clk-at91-sama7g5-remove-prescaler-part-of-master-clo.patch | |
parent | 3ed992a99630457f660761ce199e3d2a00f06168 (diff) | |
download | upstream-e58cd453d58b20c6a6f34d3591640aa19aa14d25.tar.gz upstream-e58cd453d58b20c6a6f34d3591640aa19aa14d25.tar.bz2 upstream-e58cd453d58b20c6a6f34d3591640aa19aa14d25.zip |
at91: add kernel support for sama7g5 soc
Add kernel support for SAMA7G5 by back-porting mainline kernel patches.
Among SAMA7G5 features could be remembered:
- ARM Cortex-A7
- double data rate multi-port dynamic RAM controller supporting DDR2,
DDR3, DDR3L, LPDDR2, LPDDR3 up to 533MHz
- peripherals for audio, video processing
- 1 gigabit + 1 megabit Ethernet controllers
- 6 CAN controllers
- trust zone support
- DVFS for CPU
- criptography IPs
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Diffstat (limited to 'target/linux/at91/patches-5.10/245-clk-at91-sama7g5-remove-prescaler-part-of-master-clo.patch')
-rw-r--r-- | target/linux/at91/patches-5.10/245-clk-at91-sama7g5-remove-prescaler-part-of-master-clo.patch | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/target/linux/at91/patches-5.10/245-clk-at91-sama7g5-remove-prescaler-part-of-master-clo.patch b/target/linux/at91/patches-5.10/245-clk-at91-sama7g5-remove-prescaler-part-of-master-clo.patch new file mode 100644 index 0000000000..fc0947db8c --- /dev/null +++ b/target/linux/at91/patches-5.10/245-clk-at91-sama7g5-remove-prescaler-part-of-master-clo.patch @@ -0,0 +1,50 @@ +From 91a49481af7332853c4c921d46aded8210572210 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea <claudiu.beznea@microchip.com> +Date: Mon, 11 Oct 2021 14:27:17 +0300 +Subject: [PATCH 245/247] clk: at91: sama7g5: remove prescaler part of master + clock + +On SAMA7G5 the prescaler part of master clock has been implemented as a +changeable one. Everytime the prescaler is changed the PMC_SR.MCKRDY bit +must be polled. Value 1 for PMC_SR.MCKRDY means the prescaler update is +done. Driver polls for this bit until it becomes 1. On SAMA7G5 it has +been discovered that in some conditions the PMC_SR.MCKRDY is not rising +but the rate it provides it's stable. The workaround is to add a timeout +when polling for PMC_SR.MCKRDY. At the moment, for SAMA7G5, the prescaler +will be removed from Linux clock tree as all the frequencies for CPU could +be obtained from PLL and also there will be less overhead when changing +frequency via DVFS. + +Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> +Link: https://lore.kernel.org/r/20211011112719.3951784-14-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> +Signed-off-by: Stephen Boyd <sboyd@kernel.org> +--- + drivers/clk/at91/sama7g5.c | 11 +---------- + 1 file changed, 1 insertion(+), 10 deletions(-) + +diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c +index c66bde6f7b47..fd9d17eabf54 100644 +--- a/drivers/clk/at91/sama7g5.c ++++ b/drivers/clk/at91/sama7g5.c +@@ -992,16 +992,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) + } + + parent_names[0] = "cpupll_divpmcck"; +- hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names, +- &mck0_layout, &mck0_characteristics, +- &pmc_mck0_lock, +- CLK_SET_RATE_PARENT, 0); +- if (IS_ERR(hw)) +- goto err_free; +- +- sama7g5_pmc->chws[PMC_CPU] = hw; +- +- hw = at91_clk_register_master_div(regmap, "mck0", "cpuck", ++ hw = at91_clk_register_master_div(regmap, "mck0", "cpupll_divpmcck", + &mck0_layout, &mck0_characteristics, + &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5); + if (IS_ERR(hw)) +-- +2.32.0 + |