diff options
| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2022-02-04 15:57:50 +0200 |
|---|---|---|
| committer | Petr Štetiar <ynezz@true.cz> | 2022-02-24 19:05:28 +0100 |
| commit | e58cd453d58b20c6a6f34d3591640aa19aa14d25 (patch) | |
| tree | a4fef5f5d79575a7a60b516482ee114c1dbc932e /target/linux/at91/patches-5.10/242-clk-at91-clk-master-fix-prescaler-logic.patch | |
| parent | 3ed992a99630457f660761ce199e3d2a00f06168 (diff) | |
| download | upstream-e58cd453d58b20c6a6f34d3591640aa19aa14d25.tar.gz upstream-e58cd453d58b20c6a6f34d3591640aa19aa14d25.tar.bz2 upstream-e58cd453d58b20c6a6f34d3591640aa19aa14d25.zip | |
at91: add kernel support for sama7g5 soc
Add kernel support for SAMA7G5 by back-porting mainline kernel patches.
Among SAMA7G5 features could be remembered:
- ARM Cortex-A7
- double data rate multi-port dynamic RAM controller supporting DDR2,
DDR3, DDR3L, LPDDR2, LPDDR3 up to 533MHz
- peripherals for audio, video processing
- 1 gigabit + 1 megabit Ethernet controllers
- 6 CAN controllers
- trust zone support
- DVFS for CPU
- criptography IPs
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Diffstat (limited to 'target/linux/at91/patches-5.10/242-clk-at91-clk-master-fix-prescaler-logic.patch')
| -rw-r--r-- | target/linux/at91/patches-5.10/242-clk-at91-clk-master-fix-prescaler-logic.patch | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/target/linux/at91/patches-5.10/242-clk-at91-clk-master-fix-prescaler-logic.patch b/target/linux/at91/patches-5.10/242-clk-at91-clk-master-fix-prescaler-logic.patch new file mode 100644 index 0000000000..3562d4ec21 --- /dev/null +++ b/target/linux/at91/patches-5.10/242-clk-at91-clk-master-fix-prescaler-logic.patch @@ -0,0 +1,34 @@ +From 4375cd63b55860f5e82618dc5f50846b3129842a Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea <claudiu.beznea@microchip.com> +Date: Mon, 11 Oct 2021 14:27:14 +0300 +Subject: [PATCH 242/247] clk: at91: clk-master: fix prescaler logic + +When prescaler value read from register is MASTER_PRES_MAX it means +that the input clock will be divided by 3. Fix the code to reflect +this. + +Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock") +Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> +Link: https://lore.kernel.org/r/20211011112719.3951784-11-claudiu.beznea@microchip.com +Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> +Signed-off-by: Stephen Boyd <sboyd@kernel.org> +--- + drivers/clk/at91/clk-master.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c +index 6da9ae34313a..e67bcd03a827 100644 +--- a/drivers/clk/at91/clk-master.c ++++ b/drivers/clk/at91/clk-master.c +@@ -386,7 +386,7 @@ static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw, + + val &= master->layout->mask; + pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; +- if (pres == 3 && characteristics->have_div3_pres) ++ if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres) + pres = 3; + else + pres = (1 << pres); +-- +2.32.0 + |