at91: add kernel support for sama7g5 soc

Add kernel support for SAMA7G5 by back-porting mainline kernel patches.
Among SAMA7G5 features could be remembered:
- ARM Cortex-A7
- double data rate multi-port dynamic RAM controller supporting DDR2,
  DDR3, DDR3L, LPDDR2, LPDDR3 up to 533MHz
- peripherals for audio, video processing
- 1 gigabit + 1 megabit Ethernet controllers
- 6 CAN controllers
- trust zone support
- DVFS for CPU
- criptography IPs

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

1 files changed, 44 insertions, 0 deletions

diff --git a/target/linux/at91/patches-5.10/240-clk-at91-clk-master-check-if-div-or-pres-is-zero.patch b/target/linux/at91/patches-5.10/240-clk-at91-clk-master-check-if-div-or-pres-is-zero.patch
new file mode 100644
index 0000000000..6bcc3df498
--- /dev/null
+++ b/target/linux/at91/patches-5.10/240-clk-at91-clk-master-check-if-div-or-pres-is-zero.patch
@@ -0,0 +1,44 @@
+From bb8e6ca274763fa98613dbe8b0833348a1d8fe4d Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <claudiu.beznea@microchip.com>
+Date: Mon, 11 Oct 2021 14:27:12 +0300
+Subject: [PATCH 240/247] clk: at91: clk-master: check if div or pres is zero
+
+Check if div or pres is zero before using it as argument for ffs().
+In case div is zero ffs() will return 0 and thus substracting from
+zero will lead to invalid values to be setup in registers.
+
+Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock")
+Fixes: 75c88143f3b87 ("clk: at91: clk-master: add master clock support for SAMA7G5")
+Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Link: https://lore.kernel.org/r/20211011112719.3951784-9-claudiu.beznea@microchip.com
+Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/at91/clk-master.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
+index 9a2c8e64cacf..2093e13b5068 100644
+--- a/drivers/clk/at91/clk-master.c
++++ b/drivers/clk/at91/clk-master.c
+@@ -344,7 +344,7 @@ static int clk_master_pres_set_rate(struct clk_hw *hw, unsigned long rate,
+ 
+ 	else if (pres == 3)
+ 		pres = MASTER_PRES_MAX;
+-	else
++	else if (pres)
+ 		pres = ffs(pres) - 1;
+ 
+ 	spin_lock_irqsave(master->lock, flags);
+@@ -757,7 +757,7 @@ static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate,
+ 
+ 	if (div == 3)
+ 		div = MASTER_PRES_MAX;
+-	else
++	else if (div)
+ 		div = ffs(div) - 1;
+ 
+ 	spin_lock_irqsave(master->lock, flags);
+-- 
+2.32.0
+