at91: add kernel support for sama7g5 soc

Add kernel support for SAMA7G5 by back-porting mainline kernel patches.
Among SAMA7G5 features could be remembered:
- ARM Cortex-A7
- double data rate multi-port dynamic RAM controller supporting DDR2,
  DDR3, DDR3L, LPDDR2, LPDDR3 up to 533MHz
- peripherals for audio, video processing
- 1 gigabit + 1 megabit Ethernet controllers
- 6 CAN controllers
- trust zone support
- DVFS for CPU
- criptography IPs

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

1 files changed, 99 insertions, 0 deletions

diff --git a/target/linux/at91/patches-5.10/213-ARM-at91-pm-add-sama7g5-ddr-phy-controller.patch b/target/linux/at91/patches-5.10/213-ARM-at91-pm-add-sama7g5-ddr-phy-controller.patch
new file mode 100644
index 0000000000..c01c952620
--- /dev/null
+++ b/target/linux/at91/patches-5.10/213-ARM-at91-pm-add-sama7g5-ddr-phy-controller.patch
@@ -0,0 +1,99 @@
+From bbbbf16c44f34a2d563fa7d71de64ffe3b4b82dc Mon Sep 17 00:00:00 2001
+From: Claudiu Beznea <claudiu.beznea@microchip.com>
+Date: Thu, 15 Apr 2021 13:50:04 +0300
+Subject: [PATCH 213/247] ARM: at91: pm: add sama7g5 ddr phy controller
+
+SAMA7G5 self-refresh procedure accesses also the DDR PHY registers.
+Adapt the code so that the at91_dt_ramc() to look also for DDR PHYs,
+in case it is mandatory.
+
+Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
+Link: https://lore.kernel.org/r/20210415105010.569620-19-claudiu.beznea@microchip.com
+---
+ arch/arm/mach-at91/pm.c | 27 +++++++++++++++++++++------
+ 1 file changed, 21 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
+index 622d68724c3f..b047a1f2ddfb 100644
+--- a/arch/arm/mach-at91/pm.c
++++ b/arch/arm/mach-at91/pm.c
+@@ -552,7 +552,12 @@ static const struct of_device_id ramc_ids[] __initconst = {
+ 	{ /*sentinel*/ }
+ };
+ 
+-static __init int at91_dt_ramc(void)
++static const struct of_device_id ramc_phy_ids[] __initconst = {
++	{ .compatible = "microchip,sama7g5-ddr3phy", },
++	{ /* Sentinel. */ },
++};
++
++static __init void at91_dt_ramc(bool phy_mandatory)
+ {
+ 	struct device_node *np;
+ 	const struct of_device_id *of_id;
+@@ -585,6 +590,16 @@ static __init int at91_dt_ramc(void)
+ 		goto unmap_ramc;
+ 	}
+ 
++	/* Lookup for DDR PHY node, if any. */
++	for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) {
++		soc_pm.data.ramc_phy = of_iomap(np, 0);
++		if (!soc_pm.data.ramc_phy)
++			panic(pr_fmt("unable to map ramc phy cpu registers\n"));
++	}
++
++	if (phy_mandatory && !soc_pm.data.ramc_phy)
++		panic(pr_fmt("DDR PHY is mandatory!\n"));
++
+ 	if (!standby) {
+ 		pr_warn("ramc no standby function available\n");
+ 		return 0;
+@@ -953,7 +968,7 @@ void __init at91rm9200_pm_init(void)
+ 	soc_pm.data.standby_mode = AT91_PM_STANDBY;
+ 	soc_pm.data.suspend_mode = AT91_PM_ULP0;
+ 
+-	ret = at91_dt_ramc();
++	ret = at91_dt_ramc(false);
+ 	if (ret)
+ 		return;
+ 
+@@ -980,7 +995,7 @@ void __init sam9x60_pm_init(void)
+ 
+ 	at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
+ 	at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
+-	ret = at91_dt_ramc();
++	ret = at91_dt_ramc(false);
+ 	if (ret)
+ 		return;
+ 
+@@ -1005,7 +1020,7 @@ void __init at91sam9_pm_init(void)
+ 	soc_pm.data.standby_mode = AT91_PM_STANDBY;
+ 	soc_pm.data.suspend_mode = AT91_PM_ULP0;
+ 
+-	ret = at91_dt_ramc();
++	ret = at91_dt_ramc(false);
+ 	if (ret)
+ 		return;
+ 
+@@ -1023,7 +1038,7 @@ void __init sama5_pm_init(void)
+ 		return;
+ 
+ 	at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
+-	ret = at91_dt_ramc();
++	ret = at91_dt_ramc(false);
+ 	if (ret)
+ 		return;
+ 
+@@ -1048,7 +1063,7 @@ void __init sama5d2_pm_init(void)
+ 
+ 	at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
+ 	at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
+-	ret = at91_dt_ramc();
++	ret = at91_dt_ramc(false);
+ 	if (ret)
+ 		return;
+ 
+-- 
+2.32.0
+