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| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2022-02-04 15:57:50 +0200 |
|---|---|---|
| committer | Petr Štetiar <ynezz@true.cz> | 2022-02-24 19:05:28 +0100 |
| commit | e58cd453d58b20c6a6f34d3591640aa19aa14d25 (patch) | |
| tree | a4fef5f5d79575a7a60b516482ee114c1dbc932e /target/linux/at91/patches-5.10/212-ARM-at91-pm-add-sama7g5-ddr-controller.patch | |
| parent | 3ed992a99630457f660761ce199e3d2a00f06168 (diff) | |
| download | upstream-e58cd453d58b20c6a6f34d3591640aa19aa14d25.tar.gz upstream-e58cd453d58b20c6a6f34d3591640aa19aa14d25.tar.bz2 upstream-e58cd453d58b20c6a6f34d3591640aa19aa14d25.zip | |
at91: add kernel support for sama7g5 soc
Add kernel support for SAMA7G5 by back-porting mainline kernel patches.
Among SAMA7G5 features could be remembered:
- ARM Cortex-A7
- double data rate multi-port dynamic RAM controller supporting DDR2,
DDR3, DDR3L, LPDDR2, LPDDR3 up to 533MHz
- peripherals for audio, video processing
- 1 gigabit + 1 megabit Ethernet controllers
- 6 CAN controllers
- trust zone support
- DVFS for CPU
- criptography IPs
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Diffstat (limited to 'target/linux/at91/patches-5.10/212-ARM-at91-pm-add-sama7g5-ddr-controller.patch')
| -rw-r--r-- | target/linux/at91/patches-5.10/212-ARM-at91-pm-add-sama7g5-ddr-controller.patch | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/target/linux/at91/patches-5.10/212-ARM-at91-pm-add-sama7g5-ddr-controller.patch b/target/linux/at91/patches-5.10/212-ARM-at91-pm-add-sama7g5-ddr-controller.patch new file mode 100644 index 0000000000..e85e55ccc6 --- /dev/null +++ b/target/linux/at91/patches-5.10/212-ARM-at91-pm-add-sama7g5-ddr-controller.patch @@ -0,0 +1,45 @@ +From 3f55310c00b8c478da1458704027036c1a414973 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea <claudiu.beznea@microchip.com> +Date: Thu, 15 Apr 2021 13:50:03 +0300 +Subject: [PATCH 212/247] ARM: at91: pm: add sama7g5 ddr controller + +Add SAMA7G5 DDR controller to the list of DDR controller compatibles. +At the moment there is no standby support. Adapt the code for this. + +Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> +Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> +Link: https://lore.kernel.org/r/20210415105010.569620-18-claudiu.beznea@microchip.com +--- + arch/arm/mach-at91/pm.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c +index 96f2be0a53cb..622d68724c3f 100644 +--- a/arch/arm/mach-at91/pm.c ++++ b/arch/arm/mach-at91/pm.c +@@ -548,6 +548,7 @@ static const struct of_device_id ramc_ids[] __initconst = { + { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, + { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, + { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, ++ { .compatible = "microchip,sama7g5-uddrc", }, + { /*sentinel*/ } + }; + +@@ -569,9 +570,11 @@ static __init int at91_dt_ramc(void) + } + + ramc = of_id->data; +- if (!standby) +- standby = ramc->idle; +- soc_pm.data.memctrl = ramc->memctrl; ++ if (ramc) { ++ if (!standby) ++ standby = ramc->idle; ++ soc_pm.data.memctrl = ramc->memctrl; ++ } + + idx++; + } +-- +2.32.0 + |