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author | Sander Vanheule <sander@svanheule.net> | 2022-06-19 12:38:49 +0200 |
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committer | Sander Vanheule <sander@svanheule.net> | 2022-07-21 20:59:51 +0200 |
commit | f8a44c22d469049edb9593322cd4111e7ea40b9b (patch) | |
tree | c72541072e4512bb8836562f621867196741bcb5 /target/linux/archs38/base-files | |
parent | 4da0b5a786ca4817c0608881c957f5023b9eb72b (diff) | |
download | upstream-f8a44c22d469049edb9593322cd4111e7ea40b9b.tar.gz upstream-f8a44c22d469049edb9593322cd4111e7ea40b9b.tar.bz2 upstream-f8a44c22d469049edb9593322cd4111e7ea40b9b.zip |
realtek: correct egress frame priority assignment
Priority values passed to the egress (TX) frame header initialiser are
invalid when smaller than 0, and should not be assigned to the frame.
Queue assignment is then left to the switch core logic.
Current code for RTL83xx forces the passed priority value to be
positive, by always masking it to the lower bits, resulting in the
priority always being set and enabled. RTL93xx code doesn't even check
the value and unconditionally assigns the (32 bit) value to the (5 bit)
QID field without masking.
Fix priority assignment by only setting the AS_QID/AS_PRI flag when a
valid value is passed, and properly mask the value to not overflow the
QID/PRI field.
For RTL839x, also assign the priority to the right part of the frame
header. Counting from the leftmost bit, AS_PRI and PRI are in bits 36
and 37-39. The means they should be assigned to the third 16 bit value,
containing bits 32-47.
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 0b35a08a057848d909156604c4391a5d9f1d97e5)
Diffstat (limited to 'target/linux/archs38/base-files')
0 files changed, 0 insertions, 0 deletions