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author | Florian Fainelli <florian@openwrt.org> | 2014-06-27 22:17:00 +0000 |
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committer | Florian Fainelli <florian@openwrt.org> | 2014-06-27 22:17:00 +0000 |
commit | 83192fa2c863e78c571940e5c7f9c77995400122 (patch) | |
tree | 021725c9a7cb30f62a60bbd2e995007340ab604a /target/linux/ar7 | |
parent | b0eae8648b2d266210940cfe9be4c29f194406b7 (diff) | |
download | upstream-83192fa2c863e78c571940e5c7f9c77995400122.tar.gz upstream-83192fa2c863e78c571940e5c7f9c77995400122.tar.bz2 upstream-83192fa2c863e78c571940e5c7f9c77995400122.zip |
ar7: backport an upstream fixing serial console
Signed-off-by: Florian Fainelli <florian@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@41363 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar7')
-rw-r--r-- | target/linux/ar7/patches-3.10/001-mips-ar7-fix-serial.patch | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/target/linux/ar7/patches-3.10/001-mips-ar7-fix-serial.patch b/target/linux/ar7/patches-3.10/001-mips-ar7-fix-serial.patch new file mode 100644 index 0000000000..f556ee2fa3 --- /dev/null +++ b/target/linux/ar7/patches-3.10/001-mips-ar7-fix-serial.patch @@ -0,0 +1,28 @@ +From 443ab715a40881d6c9ba11b027ba154bac904cb0 Mon Sep 17 00:00:00 2001
+From: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
+Date: Sat, 10 May 2014 23:19:08 +0200
+Subject: [PATCH] MIPS/AR7: ensure that serial ports are properly set up
+
+without UPF_FIXED_TYPE, the data from the PORT_AR7 uart_config entry is
+never copied, resulting in a dead port.
+
+Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
+---
+ arch/mips/ar7/platform.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
+index 7e2356f..e4f47d3 100644
+--- a/arch/mips/ar7/platform.c
++++ b/arch/mips/ar7/platform.c
+@@ -581,6 +581,7 @@ static int __init ar7_register_uarts(void)
+ uart_port.type = PORT_AR7;
+ uart_port.uartclk = clk_get_rate(bus_clk) / 2;
+ uart_port.iotype = UPIO_MEM32;
++ uart_port.flags = UPF_FIXED_TYPE;
+ uart_port.regshift = 2;
+
+ uart_port.line = 0;
+--
+1.8.5.3.2.g3dbf181
+
|