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| author | Gabor Juhos <juhosg@openwrt.org> | 2013-01-01 13:10:26 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2013-01-01 13:10:26 +0000 |
| commit | 93c322cacc0ccea38ebc94e4cc523e2201b88735 (patch) | |
| tree | 3e2e37a248098dee1b6a4520cfee83afaf2be826 /target/linux/ar71xx | |
| parent | b57cc9a538241451cd30f9c1f1c52e0ea01924a3 (diff) | |
| download | upstream-93c322cacc0ccea38ebc94e4cc523e2201b88735.tar.gz upstream-93c322cacc0ccea38ebc94e4cc523e2201b88735.tar.bz2 upstream-93c322cacc0ccea38ebc94e4cc523e2201b88735.zip | |
ar71xx: fix NAND controller base for QCA955x SoCs
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 34942
Diffstat (limited to 'target/linux/ar71xx')
| -rw-r--r-- | target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch | 2 | ||||
| -rw-r--r-- | target/linux/ar71xx/patches-3.7/601-MIPS-ath79-add-more-register-defines.patch | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch index 407de36008..26c87c8ef2 100644 --- a/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch @@ -50,7 +50,7 @@ #define QCA955X_EHCI_SIZE 0x200 +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA955X_GMAC_SIZE 0x40 -+#define QCA955X_NFC_BASE 0x1b000200 ++#define QCA955X_NFC_BASE 0x1b800200 +#define QCA955X_NFC_SIZE 0xb8 #define AR9300_OTP_BASE 0x14000 diff --git a/target/linux/ar71xx/patches-3.7/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.7/601-MIPS-ath79-add-more-register-defines.patch index 38290e8857..aa962059b7 100644 --- a/target/linux/ar71xx/patches-3.7/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-3.7/601-MIPS-ath79-add-more-register-defines.patch @@ -48,7 +48,7 @@ #define QCA955X_EHCI_SIZE 0x200 +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA955X_GMAC_SIZE 0x40 -+#define QCA955X_NFC_BASE 0x1b000200 ++#define QCA955X_NFC_BASE 0x1b800200 +#define QCA955X_NFC_SIZE 0xb8 #define AR9300_OTP_BASE 0x14000 |