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| author | Gabor Juhos <juhosg@openwrt.org> | 2008-11-27 17:31:22 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2008-11-27 17:31:22 +0000 |
| commit | af8da9031ff6ccc030ffad0a1b9eadad15057596 (patch) | |
| tree | 3dad49d89c79e32371f3f0e19fa54283f2551513 /target/linux/ar71xx | |
| parent | 27cbe5f744872d20b28b745b64a0f09918d16e41 (diff) | |
| download | upstream-af8da9031ff6ccc030ffad0a1b9eadad15057596.tar.gz upstream-af8da9031ff6ccc030ffad0a1b9eadad15057596.tar.bz2 upstream-af8da9031ff6ccc030ffad0a1b9eadad15057596.zip | |
[ar71xx] ag71xx driver: introduce new flag for the AR913x SOCs
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13376 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ar71xx/platform.c | 2 | ||||
| -rw-r--r-- | target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/platform.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/platform.c b/target/linux/ar71xx/files/arch/mips/ar71xx/platform.c index b2add194f7..09e6b2b78f 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/platform.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/platform.c @@ -393,6 +393,7 @@ void __init ar71xx_add_device_eth(unsigned int id) : ar91xx_ddr_flush_ge0; pdata->set_pll = id ? ar91xx_set_pll_ge1 : ar91xx_set_pll_ge0; + pdata->is_ar91xx = 1; break; case AR71XX_SOC_AR9132: @@ -400,6 +401,7 @@ void __init ar71xx_add_device_eth(unsigned int id) : ar91xx_ddr_flush_ge0; pdata->set_pll = id ? ar91xx_set_pll_ge1 : ar91xx_set_pll_ge0; + pdata->is_ar91xx = 1; pdata->has_gbit = 1; break; diff --git a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/platform.h b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/platform.h index 9d567a6c8d..2840c4567a 100644 --- a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/platform.h +++ b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/platform.h @@ -29,6 +29,7 @@ struct ag71xx_platform_data { u8 mac_addr[ETH_ALEN]; u8 has_gbit:1; + u8 is_ar91xx:1; void (* ddr_flush)(void); void (* set_pll)(u32 pll); |