diff options
| author | Felix Fietkau <nbd@openwrt.org> | 2010-12-04 01:32:15 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2010-12-04 01:32:15 +0000 |
| commit | 0b2bc8bac8175266a732596b61f16b46f204cb73 (patch) | |
| tree | cd61a73419c461e8d9d519f0efcba26c2cab4931 /target/linux/ar71xx | |
| parent | 4fd20e8c50b204be6f1a33a9d27114b8871b2a5d (diff) | |
| download | upstream-0b2bc8bac8175266a732596b61f16b46f204cb73.tar.gz upstream-0b2bc8bac8175266a732596b61f16b46f204cb73.tar.bz2 upstream-0b2bc8bac8175266a732596b61f16b46f204cb73.zip | |
ar71xx: work around a PCI controller bug which causes reads to the PCI_COMMAND register to return bogus values - properly fixes ath9k module reload issues
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@24236 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c index c6c6e55834..5f10d6a652 100644 --- a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c +++ b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c @@ -136,6 +136,7 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; unsigned long flags; u32 data; + int retry = 0; int ret; ret = PCIBIOS_SUCCESSFUL; @@ -143,6 +144,7 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); +retry: spin_lock_irqsave(&ar71xx_pci_lock, flags); if (bus->number == 0 && devfn == 0) { @@ -176,6 +178,14 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, *value = (data >> (8 * (where & 3))) & mask[size & 7]; + /* + * PCI controller bug: sometimes reads to the PCI_COMMAND register + * return 0xffff, even though the PCI trace shows the correct value. + * Work around this by retrying reads to this register + */ + if (where == PCI_COMMAND && (*value & 0xffff) == 0xffff && retry++ < 2) + goto retry; + return ret; } |