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author | Gabor Juhos <juhosg@freemail.hu> | 2018-01-15 23:04:37 +0100 |
---|---|---|
committer | John Crispin <john@phrozen.org> | 2018-01-17 11:07:17 +0100 |
commit | 508999d366b0ba378e88ce6eb500522be8eaf36f (patch) | |
tree | 0a3a538bfbfef2bf51260f0fd63ca68b0f3c3ee0 /target/linux/ar71xx/patches-4.9/741-MIPS-ath79-add-PCI-for-QCA9556-SoC.patch | |
parent | bc178f6b15c6bca292fa19982e4189f6ca7c64d4 (diff) | |
download | upstream-508999d366b0ba378e88ce6eb500522be8eaf36f.tar.gz upstream-508999d366b0ba378e88ce6eb500522be8eaf36f.tar.bz2 upstream-508999d366b0ba378e88ce6eb500522be8eaf36f.zip |
ar71xx: fix format of the 741-MIPS-ath79-add-PCI-for-QCA9556-SoC patches
The patches introduced in commit 20e68f6d395d ("ar71xx: kernel: enable
PCI on QCA9556 SoC") have non standard format. In unified diff format,
the unchanged, contextual lines must be preceded by a space character.
Refresh the patches with quilt to fix them.
Fixes: 20e68f6d395d ("ar71xx: kernel: enable PCI on QCA9556 SoC")
Signed-off-by: Gabor Juhos <juhosg@freemail.hu>
Diffstat (limited to 'target/linux/ar71xx/patches-4.9/741-MIPS-ath79-add-PCI-for-QCA9556-SoC.patch')
-rw-r--r-- | target/linux/ar71xx/patches-4.9/741-MIPS-ath79-add-PCI-for-QCA9556-SoC.patch | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/target/linux/ar71xx/patches-4.9/741-MIPS-ath79-add-PCI-for-QCA9556-SoC.patch b/target/linux/ar71xx/patches-4.9/741-MIPS-ath79-add-PCI-for-QCA9556-SoC.patch index 3a6438ee89..5ca0784253 100644 --- a/target/linux/ar71xx/patches-4.9/741-MIPS-ath79-add-PCI-for-QCA9556-SoC.patch +++ b/target/linux/ar71xx/patches-4.9/741-MIPS-ath79-add-PCI-for-QCA9556-SoC.patch @@ -1,12 +1,12 @@ --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -324,7 +324,8 @@ int __init ath79_register_pci(void) - QCA953X_PCI_MEM_SIZE, - 0, - ATH79_IP2_IRQ(0)); + QCA953X_PCI_MEM_SIZE, + 0, + ATH79_IP2_IRQ(0)); - } else if (soc_is_qca9558()) { + } else if (soc_is_qca9558() || + soc_is_qca9556()) { - pdev = ath79_register_pci_ar724x(0, - QCA955X_PCI_CFG_BASE0, - QCA955X_PCI_CTRL_BASE0, + pdev = ath79_register_pci_ar724x(0, + QCA955X_PCI_CFG_BASE0, + QCA955X_PCI_CTRL_BASE0, |