diff options
| author | Hauke Mehrtens <hauke@hauke-m.de> | 2017-10-03 18:02:59 +0200 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2017-10-11 22:32:39 +0200 |
| commit | 7bbf4117c6fe4b764d9d7c62fb2bcf6dd93bff2c (patch) | |
| tree | e42a4555f9845f78fb9baf7102da8d3d45adfacc /target/linux/ar71xx/patches-4.9/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch | |
| parent | 2909a4b78e2bce5f6b9c35361866d5e9477a1bdc (diff) | |
| download | upstream-7bbf4117c6fe4b764d9d7c62fb2bcf6dd93bff2c.tar.gz upstream-7bbf4117c6fe4b764d9d7c62fb2bcf6dd93bff2c.tar.bz2 upstream-7bbf4117c6fe4b764d9d7c62fb2bcf6dd93bff2c.zip | |
ar71xx: Add kernel 4.9 support
This add support for kernel 4.9 to the ar71xx target.
It was compile tested with the generic, NAND and mikrotik subtarget.
Multiple members of the community tested it on their boards and did not
report any major problem so far.
Especially the NAND part received some changes to adapt to the new
kernel APIs. The serial driver hack used for the Arduino Yun was not
ported because the kernel changed there a lot.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Diffstat (limited to 'target/linux/ar71xx/patches-4.9/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-4.9/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-4.9/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.9/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch new file mode 100644 index 0000000000..cab2f6f9cb --- /dev/null +++ b/target/linux/ar71xx/patches-4.9/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch @@ -0,0 +1,38 @@ +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -157,6 +157,10 @@ + #define QCA956X_EHCI0_BASE 0x1b000000 + #define QCA956X_EHCI1_BASE 0x1b400000 + #define QCA956X_EHCI_SIZE 0x200 ++#define QCA956X_GMAC_SGMII_BASE (AR71XX_APB_BASE + 0x00070000) ++#define QCA956X_GMAC_SGMII_SIZE 0x64 ++#define QCA956X_PLL_BASE (AR71XX_APB_BASE + 0x00050000) ++#define QCA956X_PLL_SIZE 0x50 + #define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) + #define QCA956X_GMAC_SIZE 0x64 + +@@ -414,6 +418,7 @@ + #define QCA956X_PLL_DDR_CONFIG_REG 0x08 + #define QCA956X_PLL_DDR_CONFIG1_REG 0x0c + #define QCA956X_PLL_CLK_CTRL_REG 0x10 ++#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30 + + #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 + #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +@@ -1196,4 +1201,16 @@ + #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 + #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 + ++/* ++ * QCA956X GMAC Interface ++ */ ++ ++#define QCA956X_GMAC_REG_ETH_CFG 0x00 ++ ++#define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7) ++#define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8) ++#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9) ++#define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10) ++#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) ++ + #endif /* __ASM_MACH_AR71XX_REGS_H */ |