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| author | Koen Vandeputte <koen.vandeputte@ncentric.com> | 2018-10-10 11:42:42 +0200 |
|---|---|---|
| committer | Koen Vandeputte <koen.vandeputte@ncentric.com> | 2018-10-10 15:12:01 +0200 |
| commit | 13f283198ef49dedd49c106176f80dfffa16c3a8 (patch) | |
| tree | 33f816b19644afca9c3798a1120007ff45441dde /target/linux/ar71xx/patches-4.9/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch | |
| parent | 77d004de6d09edc6d8a5cf77471d52d4865ae577 (diff) | |
| download | upstream-13f283198ef49dedd49c106176f80dfffa16c3a8.tar.gz upstream-13f283198ef49dedd49c106176f80dfffa16c3a8.tar.bz2 upstream-13f283198ef49dedd49c106176f80dfffa16c3a8.zip | |
ar71xx: remove linux 4.9 support
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
Diffstat (limited to 'target/linux/ar71xx/patches-4.9/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-4.9/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch | 38 |
1 files changed, 0 insertions, 38 deletions
diff --git a/target/linux/ar71xx/patches-4.9/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.9/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch deleted file mode 100644 index cab2f6f9cb..0000000000 --- a/target/linux/ar71xx/patches-4.9/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch +++ /dev/null @@ -1,38 +0,0 @@ ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -157,6 +157,10 @@ - #define QCA956X_EHCI0_BASE 0x1b000000 - #define QCA956X_EHCI1_BASE 0x1b400000 - #define QCA956X_EHCI_SIZE 0x200 -+#define QCA956X_GMAC_SGMII_BASE (AR71XX_APB_BASE + 0x00070000) -+#define QCA956X_GMAC_SGMII_SIZE 0x64 -+#define QCA956X_PLL_BASE (AR71XX_APB_BASE + 0x00050000) -+#define QCA956X_PLL_SIZE 0x50 - #define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) - #define QCA956X_GMAC_SIZE 0x64 - -@@ -414,6 +418,7 @@ - #define QCA956X_PLL_DDR_CONFIG_REG 0x08 - #define QCA956X_PLL_DDR_CONFIG1_REG 0x0c - #define QCA956X_PLL_CLK_CTRL_REG 0x10 -+#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30 - - #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 - #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -@@ -1196,4 +1201,16 @@ - #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 - #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 - -+/* -+ * QCA956X GMAC Interface -+ */ -+ -+#define QCA956X_GMAC_REG_ETH_CFG 0x00 -+ -+#define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7) -+#define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8) -+#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9) -+#define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10) -+#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) -+ - #endif /* __ASM_MACH_AR71XX_REGS_H */ |