diff options
| author | Sven Eckelmann <sven@narfation.org> | 2018-01-19 14:02:09 +0100 |
|---|---|---|
| committer | Piotr Dymacz <pepe2k@gmail.com> | 2018-02-22 18:53:22 +0100 |
| commit | b1d57dadb2da0e010e157fd2383523578c9dcc2e (patch) | |
| tree | faabe75d5b6a9d5fbad77f0eb252eef998257a2b /target/linux/ar71xx/patches-4.9/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch | |
| parent | c6bd0b48940cfbabe3fd7f9e46d125316119a7e4 (diff) | |
| download | upstream-b1d57dadb2da0e010e157fd2383523578c9dcc2e.tar.gz upstream-b1d57dadb2da0e010e157fd2383523578c9dcc2e.tar.bz2 upstream-b1d57dadb2da0e010e157fd2383523578c9dcc2e.zip | |
ar71xx: disable 40Mhz refclk for QCA953x
The "QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms"
datasheet (80-Y7991-1 Rev. C - October 2014) doesn't specify support for a
40 Mhz reference clock. The register description for "Bootstrap Options"
(page 31) defines following states for the bit 4 (REF_CLK):
* 0 - CLK25 (default)
* 1 - (reserved)
Devices like the TP-Link CPE210 v2 has this bit set to 1 but is using a 25
Mhz reference clock. OpenWrt is still interpreted this bit as 40 Mhz and
then break the bootup of the system due to this incorrect interpretation.
Signed-off-by: Sven Eckelmann <sven@narfation.org>
[refreshed patches]
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
Diffstat (limited to 'target/linux/ar71xx/patches-4.9/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-4.9/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/ar71xx/patches-4.9/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.9/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch index e6eaa7123a..03bb9c31f6 100644 --- a/target/linux/ar71xx/patches-4.9/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch +++ b/target/linux/ar71xx/patches-4.9/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch @@ -24,7 +24,7 @@ config ATH79_NVRAM --- a/arch/mips/ath79/clock.c +++ b/arch/mips/ath79/clock.c -@@ -528,6 +528,100 @@ static void __init qca955x_clocks_init(v +@@ -524,6 +524,100 @@ static void __init qca955x_clocks_init(v clk_add_alias("uart", NULL, "ref", NULL); } @@ -125,7 +125,7 @@ void __init ath79_clocks_init(void) { if (soc_is_ar71xx()) -@@ -542,6 +636,8 @@ void __init ath79_clocks_init(void) +@@ -538,6 +632,8 @@ void __init ath79_clocks_init(void) qca953x_clocks_init(); else if (soc_is_qca955x()) qca955x_clocks_init(); @@ -219,7 +219,7 @@ } --- a/arch/mips/ath79/dev-wmac.c +++ b/arch/mips/ath79/dev-wmac.c -@@ -200,6 +200,26 @@ static void qca955x_wmac_setup(void) +@@ -195,6 +195,26 @@ static void qca955x_wmac_setup(void) #define AR93XX_OTP_READ_DATA \ (soc_is_ar934x() ? AR934X_OTP_READ_DATA : AR9300_OTP_READ_DATA) @@ -246,7 +246,7 @@ static bool __init ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data) { -@@ -403,6 +423,8 @@ void __init ath79_register_wmac(u8 *cal_ +@@ -398,6 +418,8 @@ void __init ath79_register_wmac(u8 *cal_ qca953x_wmac_setup(); else if (soc_is_qca955x()) qca955x_wmac_setup(); |