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| author | Hauke Mehrtens <hauke@hauke-m.de> | 2017-10-03 18:02:59 +0200 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2017-10-11 22:32:39 +0200 |
| commit | 7bbf4117c6fe4b764d9d7c62fb2bcf6dd93bff2c (patch) | |
| tree | e42a4555f9845f78fb9baf7102da8d3d45adfacc /target/linux/ar71xx/patches-4.9/461-spi-ath79-add-fast-flash-read.patch | |
| parent | 2909a4b78e2bce5f6b9c35361866d5e9477a1bdc (diff) | |
| download | upstream-7bbf4117c6fe4b764d9d7c62fb2bcf6dd93bff2c.tar.gz upstream-7bbf4117c6fe4b764d9d7c62fb2bcf6dd93bff2c.tar.bz2 upstream-7bbf4117c6fe4b764d9d7c62fb2bcf6dd93bff2c.zip | |
ar71xx: Add kernel 4.9 support
This add support for kernel 4.9 to the ar71xx target.
It was compile tested with the generic, NAND and mikrotik subtarget.
Multiple members of the community tested it on their boards and did not
report any major problem so far.
Especially the NAND part received some changes to adapt to the new
kernel APIs. The serial driver hack used for the Arduino Yun was not
ported because the kernel changed there a lot.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Diffstat (limited to 'target/linux/ar71xx/patches-4.9/461-spi-ath79-add-fast-flash-read.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-4.9/461-spi-ath79-add-fast-flash-read.patch | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-4.9/461-spi-ath79-add-fast-flash-read.patch b/target/linux/ar71xx/patches-4.9/461-spi-ath79-add-fast-flash-read.patch new file mode 100644 index 0000000000..0dc73a8b5b --- /dev/null +++ b/target/linux/ar71xx/patches-4.9/461-spi-ath79-add-fast-flash-read.patch @@ -0,0 +1,54 @@ +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -102,9 +102,6 @@ static void ath79_spi_enable(struct ath7 + /* save CTRL register */ + sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); + sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); +- +- /* TODO: setup speed? */ +- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); + } + + static void ath79_spi_disable(struct ath79_spi *sp) +@@ -205,6 +202,33 @@ static u32 ath79_spi_txrx_mode0(struct s + return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); + } + ++static int ath79_spi_read_flash_data(struct spi_device *spi, ++ struct spi_flash_read_message *msg) ++{ ++ struct ath79_spi *sp = ath79_spidev_to_sp(spi); ++ ++ if (msg->addr_width > 3) ++ return -EOPNOTSUPP; ++ ++ if (spi->chip_select || gpio_is_valid(spi->cs_gpio)) ++ return -EOPNOTSUPP; ++ ++ /* disable GPIO mode */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); ++ ++ memcpy_fromio(msg->buf, sp->base + msg->from, msg->len); ++ ++ /* enable GPIO mode */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); ++ ++ /* restore IOC register */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); ++ ++ msg->retlen = msg->len; ++ ++ return 0; ++} ++ + static int ath79_spi_probe(struct platform_device *pdev) + { + struct spi_master *master; +@@ -234,6 +258,7 @@ static int ath79_spi_probe(struct platfo + master->num_chipselect = pdata->num_chipselect; + master->cs_gpios = pdata->cs_gpios; + } ++ master->spi_flash_read = ath79_spi_read_flash_data; + + sp->bitbang.master = master; + sp->bitbang.chipselect = ath79_spi_chipselect; |