diff options
| author | Mathias Kresin <dev@kresin.me> | 2017-03-30 22:01:09 +0200 |
|---|---|---|
| committer | Mathias Kresin <dev@kresin.me> | 2017-06-24 22:36:38 +0200 |
| commit | 0605b15be405ddaf9499e02f4b5a59ba406d2ccd (patch) | |
| tree | 0427a40d591ae014d1e9ae77fc08c88b72113754 /target/linux/ar71xx/patches-4.4/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch | |
| parent | 8e0d7d6574139e1ab4f99926e2cd09f6959d1073 (diff) | |
| download | upstream-0605b15be405ddaf9499e02f4b5a59ba406d2ccd.tar.gz upstream-0605b15be405ddaf9499e02f4b5a59ba406d2ccd.tar.bz2 upstream-0605b15be405ddaf9499e02f4b5a59ba406d2ccd.zip | |
ar71xx: add AR724x PCIe init fixes
Add upstream send AR724x PCIe patches to get the PCIe controller out of
reset during driver init.
The AVM Fritz 300E bootloader doesn't take care of releasing the
different PCIe controller related resets which causes an endless hang
as soon as either the PCIE Reset register (0x180f0018) or the PCI
Application Control register (0x180f0000) is read from.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Diffstat (limited to 'target/linux/ar71xx/patches-4.4/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-4.4/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/target/linux/ar71xx/patches-4.4/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.4/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch index d8bb248a14..1f3a19886d 100644 --- a/target/linux/ar71xx/patches-4.4/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch +++ b/target/linux/ar71xx/patches-4.4/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch @@ -522,7 +522,7 @@ * DDR_CTRL block */ #define AR71XX_DDR_REG_PCI_WIN0 0x7c -@@ -382,6 +406,49 @@ +@@ -385,6 +409,49 @@ #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) @@ -572,7 +572,7 @@ /* * USB_CONFIG block */ -@@ -429,6 +496,11 @@ +@@ -432,6 +499,11 @@ #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac @@ -584,7 +584,7 @@ #define MISC_INT_ETHSW BIT(12) #define MISC_INT_TIMER4 BIT(10) #define MISC_INT_TIMER3 BIT(9) -@@ -603,6 +675,8 @@ +@@ -606,6 +678,8 @@ #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) @@ -593,7 +593,7 @@ #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) -@@ -670,6 +744,37 @@ +@@ -673,6 +747,37 @@ QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ QCA955X_EXT_INT_PCIE_RC2_INT3) @@ -631,7 +631,7 @@ #define REV_ID_MAJOR_MASK 0xfff0 #define REV_ID_MAJOR_AR71XX 0x00a0 #define REV_ID_MAJOR_AR913X 0x00b0 -@@ -685,6 +790,8 @@ +@@ -688,6 +793,8 @@ #define REV_ID_MAJOR_QCA9533_V2 0x0160 #define REV_ID_MAJOR_QCA9556 0x0130 #define REV_ID_MAJOR_QCA9558 0x1130 @@ -640,7 +640,7 @@ #define AR71XX_REV_ID_MINOR_MASK 0x3 #define AR71XX_REV_ID_MINOR_AR7130 0x0 -@@ -709,6 +816,8 @@ +@@ -712,6 +819,8 @@ #define QCA955X_REV_ID_REVISION_MASK 0xf @@ -649,7 +649,7 @@ /* * SPI block */ -@@ -781,6 +890,19 @@ +@@ -784,6 +893,19 @@ #define QCA955X_GPIO_REG_OUT_FUNC5 0x40 #define QCA955X_GPIO_REG_FUNC 0x6c @@ -669,7 +669,7 @@ #define AR71XX_GPIO_COUNT 16 #define AR7240_GPIO_COUNT 18 #define AR7241_GPIO_COUNT 20 -@@ -789,6 +911,7 @@ +@@ -792,6 +914,7 @@ #define AR934X_GPIO_COUNT 23 #define QCA953X_GPIO_COUNT 18 #define QCA955X_GPIO_COUNT 24 |