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| author | Stijn Tintel <stijn@linux-ipv6.be> | 2017-06-27 07:41:10 +0200 |
|---|---|---|
| committer | Stijn Tintel <stijn@linux-ipv6.be> | 2017-06-27 07:42:50 +0200 |
| commit | f80963d4d18d67c3190d40b7eadaa0e427ccbf7b (patch) | |
| tree | ba55ebb12fa4d23df373ee18c61fc9ff6437dd09 /target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch | |
| parent | 69649a1b45ee0ab7ab3de350dc75f89d867c174c (diff) | |
| download | upstream-f80963d4d18d67c3190d40b7eadaa0e427ccbf7b.tar.gz upstream-f80963d4d18d67c3190d40b7eadaa0e427ccbf7b.tar.bz2 upstream-f80963d4d18d67c3190d40b7eadaa0e427ccbf7b.zip | |
kernel: update kernel 4.4 to 4.4.74
Refresh patches.
Compile-tested on ar71xx.
Runtime-tested on ar71xx.
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Diffstat (limited to 'target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch index d117f94021..5cfb4e78d7 100644 --- a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch +++ b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch @@ -229,7 +229,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. else --- a/arch/mips/ath79/dev-wmac.c +++ b/arch/mips/ath79/dev-wmac.c -@@ -101,7 +101,7 @@ static int ar933x_wmac_reset(void) +@@ -100,7 +100,7 @@ static int ar933x_wmac_reset(void) return -ETIMEDOUT; } @@ -238,7 +238,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. { return ath79_soc_rev; } -@@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(voi +@@ -125,7 +125,7 @@ static void __init ar933x_wmac_setup(voi ath79_wmac_data.is_clk_25mhz = true; if (ath79_soc_rev == 1) @@ -247,7 +247,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. ath79_wmac_data.external_reset = ar933x_wmac_reset; } -@@ -151,6 +151,26 @@ static void ar934x_wmac_setup(void) +@@ -150,6 +150,26 @@ static void ar934x_wmac_setup(void) ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision; } @@ -274,7 +274,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. static void qca955x_wmac_setup(void) { u32 t; -@@ -380,6 +400,8 @@ void __init ath79_register_wmac(u8 *cal_ +@@ -379,6 +399,8 @@ void __init ath79_register_wmac(u8 *cal_ ar933x_wmac_setup(); else if (soc_is_ar934x()) ar934x_wmac_setup(); |