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| author | Felix Fietkau <nbd@nbd.name> | 2016-05-14 20:24:37 +0200 |
|---|---|---|
| committer | Felix Fietkau <nbd@nbd.name> | 2016-05-15 20:55:39 +0200 |
| commit | 5b34dffcbd6175d92f871b69098e027341b6c82e (patch) | |
| tree | 4435dd82308ac86ab73aaaf8de0b83d223ab8b2b /target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch | |
| parent | e30608b736f44e70da6bd29fbcfdc9dd5ec42f02 (diff) | |
| download | upstream-5b34dffcbd6175d92f871b69098e027341b6c82e.tar.gz upstream-5b34dffcbd6175d92f871b69098e027341b6c82e.tar.bz2 upstream-5b34dffcbd6175d92f871b69098e027341b6c82e.zip | |
ar71xx: fix DDR write buffer flushing issues with 4.4
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch index 6fd6dafd47..08a684becd 100644 --- a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch +++ b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch @@ -335,10 +335,10 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. + status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS); + + if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) { -+ ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_PCIE); ++ ath79_ddr_wb_flush(3); + generic_handle_irq(ATH79_IP2_IRQ(0)); + } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) { -+ ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_WMAC); ++ ath79_ddr_wb_flush(4); + generic_handle_irq(ATH79_IP2_IRQ(1)); + } else { + spurious_interrupt(); |