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| author | Mathias Kresin <dev@kresin.me> | 2017-03-30 22:01:09 +0200 |
|---|---|---|
| committer | Mathias Kresin <dev@kresin.me> | 2017-06-24 22:36:38 +0200 |
| commit | 0605b15be405ddaf9499e02f4b5a59ba406d2ccd (patch) | |
| tree | 0427a40d591ae014d1e9ae77fc08c88b72113754 /target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch | |
| parent | 8e0d7d6574139e1ab4f99926e2cd09f6959d1073 (diff) | |
| download | upstream-0605b15be405ddaf9499e02f4b5a59ba406d2ccd.tar.gz upstream-0605b15be405ddaf9499e02f4b5a59ba406d2ccd.tar.bz2 upstream-0605b15be405ddaf9499e02f4b5a59ba406d2ccd.zip | |
ar71xx: add AR724x PCIe init fixes
Add upstream send AR724x PCIe patches to get the PCIe controller out of
reset during driver init.
The AVM Fritz 300E bootloader doesn't take care of releasing the
different PCIe controller related resets which causes an endless hang
as soon as either the PCIE Reset register (0x180f0018) or the PCI
Application Control register (0x180f0000) is read from.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Diffstat (limited to 'target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch index e4d82acf5e..d0f5b78901 100644 --- a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch @@ -66,9 +66,9 @@ +#define AR71XX_ETH1_PLL_SHIFT 19 + #define AR724X_PLL_REG_CPU_CONFIG 0x00 - #define AR724X_PLL_REG_PCIE_CONFIG 0x18 + #define AR724X_PLL_REG_PCIE_CONFIG 0x10 -@@ -193,6 +212,8 @@ +@@ -196,6 +215,8 @@ #define AR724X_DDR_DIV_SHIFT 22 #define AR724X_DDR_DIV_MASK 0x3 @@ -77,7 +77,7 @@ #define AR913X_PLL_REG_CPU_CONFIG 0x00 #define AR913X_PLL_REG_ETH_CONFIG 0x04 #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 -@@ -205,6 +226,9 @@ +@@ -208,6 +229,9 @@ #define AR913X_AHB_DIV_SHIFT 19 #define AR913X_AHB_DIV_MASK 0x1 @@ -87,7 +87,7 @@ #define AR933X_PLL_CPU_CONFIG_REG 0x00 #define AR933X_PLL_CLOCK_CTRL_REG 0x08 -@@ -226,6 +250,8 @@ +@@ -229,6 +253,8 @@ #define AR934X_PLL_CPU_CONFIG_REG 0x00 #define AR934X_PLL_DDR_CONFIG_REG 0x04 #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 @@ -96,7 +96,7 @@ #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -@@ -258,9 +284,13 @@ +@@ -261,9 +287,13 @@ #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) @@ -110,7 +110,7 @@ #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -@@ -385,16 +415,83 @@ +@@ -388,16 +418,83 @@ #define AR913X_RESET_USB_HOST BIT(5) #define AR913X_RESET_USB_PHY BIT(4) @@ -194,7 +194,7 @@ #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) -@@ -536,8 +633,22 @@ +@@ -539,8 +636,22 @@ #define AR71XX_GPIO_REG_INT_ENABLE 0x24 #define AR71XX_GPIO_REG_FUNC 0x28 @@ -217,7 +217,7 @@ #define AR71XX_GPIO_COUNT 16 #define AR7240_GPIO_COUNT 18 #define AR7241_GPIO_COUNT 20 -@@ -567,4 +678,235 @@ +@@ -570,4 +681,235 @@ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 |