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authorFelix Fietkau <nbd@nbd.name>2016-12-08 21:10:50 +0100
committerFelix Fietkau <nbd@nbd.name>2016-12-12 10:22:17 +0100
commitfa04682f213f81840ca17022ca5aa9439bc22f2c (patch)
tree7df5bbad4ef622683414f6b1aa4f084845e0fbf3 /target/linux/ar71xx/patches-4.4/461-spi-ath79-add-fast-flash-read.patch
parent52c7375c134afd204f6ac9d46265f77f7800123c (diff)
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ar71xx: clean up spi controller related patches
Remove various hacks for fast read, un-break device tree support Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'target/linux/ar71xx/patches-4.4/461-spi-ath79-add-fast-flash-read.patch')
-rw-r--r--target/linux/ar71xx/patches-4.4/461-spi-ath79-add-fast-flash-read.patch54
1 files changed, 54 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-4.4/461-spi-ath79-add-fast-flash-read.patch b/target/linux/ar71xx/patches-4.4/461-spi-ath79-add-fast-flash-read.patch
new file mode 100644
index 0000000000..0dc73a8b5b
--- /dev/null
+++ b/target/linux/ar71xx/patches-4.4/461-spi-ath79-add-fast-flash-read.patch
@@ -0,0 +1,54 @@
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -102,9 +102,6 @@ static void ath79_spi_enable(struct ath7
+ /* save CTRL register */
+ sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
+ sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
+-
+- /* TODO: setup speed? */
+- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
+ }
+
+ static void ath79_spi_disable(struct ath79_spi *sp)
+@@ -205,6 +202,33 @@ static u32 ath79_spi_txrx_mode0(struct s
+ return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
+ }
+
++static int ath79_spi_read_flash_data(struct spi_device *spi,
++ struct spi_flash_read_message *msg)
++{
++ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
++
++ if (msg->addr_width > 3)
++ return -EOPNOTSUPP;
++
++ if (spi->chip_select || gpio_is_valid(spi->cs_gpio))
++ return -EOPNOTSUPP;
++
++ /* disable GPIO mode */
++ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
++
++ memcpy_fromio(msg->buf, sp->base + msg->from, msg->len);
++
++ /* enable GPIO mode */
++ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
++
++ /* restore IOC register */
++ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
++
++ msg->retlen = msg->len;
++
++ return 0;
++}
++
+ static int ath79_spi_probe(struct platform_device *pdev)
+ {
+ struct spi_master *master;
+@@ -234,6 +258,7 @@ static int ath79_spi_probe(struct platfo
+ master->num_chipselect = pdata->num_chipselect;
+ master->cs_gpios = pdata->cs_gpios;
+ }
++ master->spi_flash_read = ath79_spi_read_flash_data;
+
+ sp->bitbang.master = master;
+ sp->bitbang.chipselect = ath79_spi_chipselect;