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authorGabor Juhos <juhosg@openwrt.org>2012-09-08 13:39:09 +0000
committerGabor Juhos <juhosg@openwrt.org>2012-09-08 13:39:09 +0000
commitf4be8a76ded14beac436192fa163d090a821b48b (patch)
tree5adac79c606f76364d145dca868c78f03b0897ae /target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch
parent70d00ac64ebfdda82900bfe6160e9f723227533e (diff)
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ar71xx: fix CPU/DDR frequency calculation for SRIF PLLs on AR934x
SVN-Revision: 33335
Diffstat (limited to 'target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch')
-rw-r--r--target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch4
1 files changed, 2 insertions, 2 deletions
diff --git a/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch b/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch
index e4e2c30d94..8d24c742d3 100644
--- a/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch
+++ b/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch
@@ -165,7 +165,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
}
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -298,6 +298,7 @@
+@@ -300,6 +300,7 @@
#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
@@ -173,7 +173,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
#define MISC_INT_ETHSW BIT(12)
#define MISC_INT_TIMER4 BIT(10)
-@@ -396,6 +397,37 @@
+@@ -398,6 +399,37 @@
AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
AR934X_PCIE_WMAC_INT_PCIE_RC3)