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| author | Felix Fietkau <nbd@openwrt.org> | 2015-07-07 08:06:05 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2015-07-07 08:06:05 +0000 |
| commit | b26077026fc0f4e99c9d4c97e71f263770615500 (patch) | |
| tree | 2c46b87f41298cf8d904b9673768e2907ade8c74 /target/linux/ar71xx/patches-3.18/811-MIPS-ath79-gpio-enable-set-direction.patch | |
| parent | c9e433206f3440e683fbf7a2334bcd32e8daba1d (diff) | |
| download | upstream-b26077026fc0f4e99c9d4c97e71f263770615500.tar.gz upstream-b26077026fc0f4e99c9d4c97e71f263770615500.tar.bz2 upstream-b26077026fc0f4e99c9d4c97e71f263770615500.zip | |
ar71xx: add support for ap143
Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
SVN-Revision: 46208
Diffstat (limited to 'target/linux/ar71xx/patches-3.18/811-MIPS-ath79-gpio-enable-set-direction.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-3.18/811-MIPS-ath79-gpio-enable-set-direction.patch | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-3.18/811-MIPS-ath79-gpio-enable-set-direction.patch b/target/linux/ar71xx/patches-3.18/811-MIPS-ath79-gpio-enable-set-direction.patch new file mode 100644 index 0000000000..f2c1f67b04 --- /dev/null +++ b/target/linux/ar71xx/patches-3.18/811-MIPS-ath79-gpio-enable-set-direction.patch @@ -0,0 +1,43 @@ +--- a/arch/mips/ath79/common.h ++++ b/arch/mips/ath79/common.h +@@ -28,6 +28,7 @@ void ath79_gpio_function_enable(u32 mask); + void ath79_gpio_function_disable(u32 mask); + void ath79_gpio_function_setup(u32 set, u32 clear); + void ath79_gpio_output_select(unsigned gpio, u8 val); ++int ath79_gpio_direction_select(unsigned gpio, bool oe); + void ath79_gpio_init(void); + + #endif /* __ATH79_COMMON_H */ +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -130,6 +130,30 @@ static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset, + return 0; + } + ++int ath79_gpio_direction_select(unsigned gpio, bool oe) ++{ ++ void __iomem *base = ath79_gpio_base; ++ unsigned long flags; ++ bool ieq_1 = (soc_is_ar934x() || ++ soc_is_qca953x()); ++ ++ if (gpio >= ath79_gpio_count) ++ return -1; ++ ++ spin_lock_irqsave(&ath79_gpio_lock, flags); ++ ++ if ((ieq_1 && oe) || (!ieq_1 && !oe)) ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << gpio), ++ base + AR71XX_GPIO_REG_OE); ++ else ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << gpio), ++ base + AR71XX_GPIO_REG_OE); ++ ++ spin_unlock_irqrestore(&ath79_gpio_lock, flags); ++ ++ return 0; ++} ++ + static struct gpio_chip ath79_gpio_chip = { + .label = "ath79", + .get = ath79_gpio_get_value, |