ar71xx: rework patch for qca953x/956x

Patch cherry-picked from the following location:
https://www.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?h=release/coconut_ioe4531_2.0&id=5c357bf6c763e4140dddcc9a3bc5f005525a9c0e

Changelist,
    - add more register defines
    - add EHCI support
    - fix GPIO pin count to 18
    - fix chained irq disabled
    - fix GMAC0/GMAC1 initial
    - fix WMAC irq number to 47
    - merge the changes of dev-eth.c from the patch to file.

Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>

Backport of r46207

git-svn-id: svn://svn.openwrt.org/openwrt/branches/chaos_calmer@48854 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 23 insertions, 90 deletions

diff --git a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
index ab2bc38d4d..eecccdcd0d 100644
--- a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
+++ b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
@@ -142,74 +142,9 @@
  		ath79_uart_data[0].uartclk = uart_clk_rate;
  		platform_device_register(&ath79_uart_device);
  	} else if (soc_is_ar933x()) {
---- a/arch/mips/ath79/dev-eth.c
-+++ b/arch/mips/ath79/dev-eth.c
-@@ -198,6 +198,8 @@ void __init ath79_register_mdio(unsigned
- 	case ATH79_SOC_AR9330:
- 	case ATH79_SOC_AR9331:
- 	case ATH79_SOC_QCA9533:
-+	case ATH79_SOC_QCA9561:
-+	case ATH79_SOC_TP9343:
- 		mdio_dev = &ath79_mdio1_device;
- 		mdio_data = &ath79_mdio1_data;
- 		break;
-@@ -256,6 +258,8 @@ void __init ath79_register_mdio(unsigned
- 		break;
- 
- 	case ATH79_SOC_QCA9533:
-+	case ATH79_SOC_QCA9561:
-+	case ATH79_SOC_TP9343:
- 		mdio_data->builtin_switch = 1;
- 		break;
- 
-@@ -571,6 +575,8 @@ static void __init ath79_init_eth_pll_da
- 	case ATH79_SOC_QCA9533:
- 	case ATH79_SOC_QCA9556:
- 	case ATH79_SOC_QCA9558:
-+	case ATH79_SOC_QCA9561:
-+	case ATH79_SOC_TP9343:
- 		pll_10 = AR934X_PLL_VAL_10;
- 		pll_100 = AR934X_PLL_VAL_100;
- 		pll_1000 = AR934X_PLL_VAL_1000;
-@@ -627,6 +633,8 @@ static int __init ath79_setup_phy_if_mod
- 		case ATH79_SOC_AR9330:
- 		case ATH79_SOC_AR9331:
- 		case ATH79_SOC_QCA9533:
-+		case ATH79_SOC_QCA9561:
-+		case ATH79_SOC_TP9343:
- 			pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
- 			break;
- 
-@@ -688,6 +696,8 @@ static int __init ath79_setup_phy_if_mod
- 		case ATH79_SOC_AR9330:
- 		case ATH79_SOC_AR9331:
- 		case ATH79_SOC_QCA9533:
-+		case ATH79_SOC_QCA9561:
-+		case ATH79_SOC_TP9343:
- 			pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
- 			break;
- 
-@@ -1018,6 +1028,8 @@ void __init ath79_register_eth(unsigned
- 		break;
- 
- 	case ATH79_SOC_QCA9533:
-+	case ATH79_SOC_QCA9561:
-+	case ATH79_SOC_TP9343:
- 		if (id == 0) {
- 			pdata->reset_bit = AR933X_RESET_GE0_MAC |
- 					   AR933X_RESET_GE0_MDIO;
-@@ -1123,6 +1135,8 @@ void __init ath79_register_eth(unsigned
- 		case ATH79_SOC_AR9330:
- 		case ATH79_SOC_AR9331:
- 		case ATH79_SOC_QCA9533:
-+		case ATH79_SOC_QCA9561:
-+		case ATH79_SOC_TP9343:
- 			pdata->mii_bus_dev = &ath79_mdio1_device.dev;
- 			break;
- 
 --- a/arch/mips/ath79/dev-usb.c
 +++ b/arch/mips/ath79/dev-usb.c
-@@ -272,6 +272,19 @@ static void __init qca955x_usb_setup(voi
+@@ -296,6 +296,19 @@ static void __init qca955x_usb_setup(voi
  			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  }
  
@@ -229,8 +164,8 @@
  void __init ath79_register_usb(void)
  {
  	if (soc_is_ar71xx())
-@@ -288,6 +301,8 @@ void __init ath79_register_usb(void)
- 		ar934x_usb_setup();
+@@ -314,6 +327,8 @@ void __init ath79_register_usb(void)
+ 		qca953x_usb_setup();
  	else if (soc_is_qca955x())
  		qca955x_usb_setup();
 +	else if (soc_is_qca9561())
@@ -291,9 +226,9 @@
  	    soc_is_ar913x() ||
  	    soc_is_ar933x())
  		reg = AR71XX_GPIO_REG_FUNC;
--	else if (soc_is_ar934x())
+-	else if (soc_is_ar934x() || soc_is_qca953x())
 +	else if (soc_is_ar934x() ||
-+		 soc_is_qca956x())
++		 soc_is_qca953x() || soc_is_qca956x())
  		reg = AR934X_GPIO_REG_FUNC;
  	else
  		BUG();
@@ -326,7 +261,7 @@
  		ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
  	else
  		BUG();
-@@ -236,6 +237,99 @@ static void qca955x_irq_init(void)
+@@ -268,6 +269,97 @@ static void qca955x_irq_init(void)
  	irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
  }
  
@@ -406,15 +341,13 @@
 +
 +	for (i = ATH79_IP2_IRQ_BASE;
 +	     i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
-+		irq_set_chip_and_handler(i, &dummy_irq_chip,
-+					 handle_level_irq);
++		irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 +
 +	irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
 +
 +	for (i = ATH79_IP3_IRQ_BASE;
 +	     i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
-+		irq_set_chip_and_handler(i, &dummy_irq_chip,
-+					 handle_level_irq);
++		irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 +
 +	irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
 +
@@ -426,7 +359,7 @@
  asmlinkage void plat_irq_dispatch(void)
  {
  	unsigned long pending;
-@@ -359,6 +453,9 @@ void __init arch_init_irq(void)
+@@ -397,6 +489,9 @@ void __init arch_init_irq(void)
  	} else if (soc_is_qca955x()) {
  		ath79_ip2_handler = ath79_default_ip2_handler;
  		ath79_ip3_handler = ath79_default_ip3_handler;
@@ -436,8 +369,8 @@
  	} else {
  		BUG();
  	}
-@@ -371,4 +468,6 @@ void __init arch_init_irq(void)
- 		ar934x_ip2_irq_init();
+@@ -411,4 +506,6 @@ void __init arch_init_irq(void)
+ 		qca953x_irq_init();
  	else if (soc_is_qca955x())
  		qca955x_irq_init();
 +	else if (soc_is_qca956x())
@@ -554,7 +487,7 @@
  	pr_info("SoC: %s\n", ath79_sys_type);
 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -131,6 +131,23 @@
+@@ -143,6 +143,23 @@
  #define QCA955X_NFC_BASE	0x1b800200
  #define QCA955X_NFC_SIZE	0xb8
  
@@ -578,7 +511,7 @@
  #define AR9300_OTP_BASE		0x14000
  #define AR9300_OTP_STATUS	0x15f18
  #define AR9300_OTP_STATUS_TYPE		0x7
-@@ -356,6 +373,49 @@
+@@ -375,6 +392,49 @@
  #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL		BIT(21)
  #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)
  
@@ -628,7 +561,7 @@
  /*
   * USB_CONFIG block
   */
-@@ -403,6 +463,11 @@
+@@ -422,6 +482,11 @@
  #define QCA955X_RESET_REG_BOOTSTRAP		0xb0
  #define QCA955X_RESET_REG_EXT_INT_STATUS	0xac
  
@@ -640,7 +573,7 @@
  #define MISC_INT_ETHSW			BIT(12)
  #define MISC_INT_TIMER4			BIT(10)
  #define MISC_INT_TIMER3			BIT(9)
-@@ -551,6 +616,8 @@
+@@ -596,6 +661,8 @@
  
  #define QCA955X_BOOTSTRAP_REF_CLK_40	BIT(4)
  
@@ -649,7 +582,7 @@
  #define AR934X_PCIE_WMAC_INT_WMAC_MISC		BIT(0)
  #define AR934X_PCIE_WMAC_INT_WMAC_TX		BIT(1)
  #define AR934X_PCIE_WMAC_INT_WMAC_RXLP		BIT(2)
-@@ -600,6 +667,37 @@
+@@ -663,6 +730,37 @@
  	 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
  	 QCA955X_EXT_INT_PCIE_RC2_INT3)
  
@@ -687,7 +620,7 @@
  #define REV_ID_MAJOR_MASK		0xfff0
  #define REV_ID_MAJOR_AR71XX		0x00a0
  #define REV_ID_MAJOR_AR913X		0x00b0
-@@ -615,6 +713,8 @@
+@@ -678,6 +776,8 @@
  #define REV_ID_MAJOR_QCA9533_V2		0x0160
  #define REV_ID_MAJOR_QCA9556		0x0130
  #define REV_ID_MAJOR_QCA9558		0x1130
@@ -696,7 +629,7 @@
  
  #define AR71XX_REV_ID_MINOR_MASK	0x3
  #define AR71XX_REV_ID_MINOR_AR7130	0x0
-@@ -639,6 +739,8 @@
+@@ -702,6 +802,8 @@
  
  #define QCA955X_REV_ID_REVISION_MASK	0xf
  
@@ -705,9 +638,9 @@
  /*
   * SPI block
   */
-@@ -684,6 +786,19 @@
- #define AR934X_GPIO_REG_OUT_FUNC5	0x40
- #define AR934X_GPIO_REG_FUNC		0x6c
+@@ -766,6 +868,19 @@
+ #define QCA953X_GPIO_OUT_MUX_LED_LINK4		44
+ #define QCA953X_GPIO_OUT_MUX_LED_LINK5		45
  
 +#define QCA956X_GPIO_REG_OUT_FUNC0	0x2c
 +#define QCA956X_GPIO_REG_OUT_FUNC1	0x30
@@ -725,9 +658,9 @@
  #define AR71XX_GPIO_COUNT		16
  #define AR7240_GPIO_COUNT		18
  #define AR7241_GPIO_COUNT		20
-@@ -692,6 +807,7 @@
+@@ -774,6 +889,7 @@
  #define AR934X_GPIO_COUNT		23
- #define QCA953X_GPIO_COUNT		24
+ #define QCA953X_GPIO_COUNT		18
  #define QCA955X_GPIO_COUNT		24
 +#define QCA956X_GPIO_COUNT		23