ar71xx: rework patch for qca953x/956x

Patch cherry-picked from the following location:
https://www.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?h=release/coconut_ioe4531_2.0&id=5c357bf6c763e4140dddcc9a3bc5f005525a9c0e

Changelist,
    - add more register defines
    - add EHCI support
    - fix GPIO pin count to 18
    - fix chained irq disabled
    - fix GMAC0/GMAC1 initial
    - fix WMAC irq number to 47
    - merge the changes of dev-eth.c from the patch to file.

Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>

Backport of r46207

git-svn-id: svn://svn.openwrt.org/openwrt/branches/chaos_calmer@48854 3c298f89-4303-0410-b956-a3cf2f4a3e73

1 files changed, 286 insertions, 14 deletions

diff --git a/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
index f3b444639d..cf10af3e22 100644
--- a/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
+++ b/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
@@ -175,6 +175,48 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  	    soc_is_qca955x()) {
  		ath79_uart_data[0].uartclk = uart_clk_rate;
  		platform_device_register(&ath79_uart_device);
+--- a/arch/mips/ath79/dev-usb.c
++++ b/arch/mips/ath79/dev-usb.c
+@@ -236,6 +236,30 @@ static void __init ar934x_usb_setup(void
+ 			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
+ }
+ 
++static void __init qca953x_usb_setup(void)
++{
++	u32 bootstrap;
++
++	bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
++
++	ath79_device_reset_set(QCA953X_RESET_USBSUS_OVERRIDE);
++	udelay(1000);
++
++	ath79_device_reset_clear(QCA953X_RESET_USB_PHY);
++	udelay(1000);
++
++	ath79_device_reset_clear(QCA953X_RESET_USB_PHY_ANALOG);
++	udelay(1000);
++
++	ath79_device_reset_clear(QCA953X_RESET_USB_HOST);
++	udelay(1000);
++
++	ath79_usb_register("ehci-platform", -1,
++			   QCA953X_EHCI_BASE, QCA953X_EHCI_SIZE,
++			   ATH79_CPU_IRQ(3),
++			   &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
++}
++
+ static void qca955x_usb_reset_notifier(struct platform_device *pdev)
+ {
+ 	u32 base;
+@@ -286,6 +310,8 @@ void __init ath79_register_usb(void)
+ 		ar933x_usb_setup();
+ 	else if (soc_is_ar934x())
+ 		ar934x_usb_setup();
++	else if (soc_is_qca953x())
++		qca953x_usb_setup();
+ 	else if (soc_is_qca955x())
+ 		qca955x_usb_setup();
+ 	else
 --- a/arch/mips/ath79/dev-wmac.c
 +++ b/arch/mips/ath79/dev-wmac.c
 @@ -101,7 +101,7 @@ static int ar933x_wmac_reset(void)
@@ -207,8 +249,8 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
 +
 +	ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
 +	ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;
-+	ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
-+	ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
++	ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
++	ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
 +
 +	t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
 +	if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
@@ -244,6 +286,24 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  		_prom_putchar = prom_putchar_ar71xx;
 --- a/arch/mips/ath79/gpio.c
 +++ b/arch/mips/ath79/gpio.c
+@@ -148,7 +148,7 @@ static void __iomem *ath79_gpio_get_func
+ 	    soc_is_ar913x() ||
+ 	    soc_is_ar933x())
+ 		reg = AR71XX_GPIO_REG_FUNC;
+-	else if (soc_is_ar934x())
++	else if (soc_is_ar934x() || soc_is_qca953x())
+ 		reg = AR934X_GPIO_REG_FUNC;
+ 	else
+ 		BUG();
+@@ -187,7 +187,7 @@ void __init ath79_gpio_output_select(uns
+ 	unsigned int reg;
+ 	u32 t, s;
+ 
+-	BUG_ON(!soc_is_ar934x());
++	BUG_ON(!soc_is_ar934x() && !soc_is_qca953x());
+ 
+ 	if (gpio >= AR934X_GPIO_COUNT)
+ 		return;
 @@ -224,6 +224,8 @@ void __init ath79_gpio_init(void)
  		ath79_gpio_count = AR933X_GPIO_COUNT;
  	else if (soc_is_ar934x())
@@ -272,16 +332,77 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  		 soc_is_qca955x())
  		ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
  	else
-@@ -352,6 +353,9 @@ void __init arch_init_irq(void)
+@@ -153,6 +154,38 @@ static void ar934x_ip2_irq_init(void)
+ 	irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
+ }
+ 
++static void qca953x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
++{
++	u32 status;
++
++	disable_irq_nosync(irq);
++
++	status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
++
++	if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
++		ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_PCIE);
++		generic_handle_irq(ATH79_IP2_IRQ(0));
++	} else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
++		ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_WMAC);
++		generic_handle_irq(ATH79_IP2_IRQ(1));
++	} else {
++		spurious_interrupt();
++	}
++
++	enable_irq(irq);
++}
++
++static void qca953x_irq_init(void)
++{
++	int i;
++
++	for (i = ATH79_IP2_IRQ_BASE;
++	     i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
++		irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
++
++	irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
++}
++
+ static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
+ {
+ 	u32 status;
+@@ -335,6 +368,12 @@ static void ar934x_ip3_handler(void)
+ 	do_IRQ(ATH79_CPU_IRQ(3));
+ }
+ 
++static void qca953x_ip3_handler(void)
++{
++	ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_USB);
++	do_IRQ(ATH79_CPU_IRQ(3));
++}
++
+ void __init arch_init_irq(void)
+ {
+ 	if (soc_is_ar71xx()) {
+@@ -352,6 +391,9 @@ void __init arch_init_irq(void)
  	} else if (soc_is_ar934x()) {
  		ath79_ip2_handler = ath79_default_ip2_handler;
  		ath79_ip3_handler = ar934x_ip3_handler;
 +	} else if (soc_is_qca953x()) {
 +		ath79_ip2_handler = ath79_default_ip2_handler;
-+		ath79_ip3_handler = ath79_default_ip3_handler;
++		ath79_ip3_handler = qca953x_ip3_handler;
  	} else if (soc_is_qca955x()) {
  		ath79_ip2_handler = ath79_default_ip2_handler;
  		ath79_ip3_handler = ath79_default_ip3_handler;
+@@ -365,6 +407,8 @@ void __init arch_init_irq(void)
+ 
+ 	if (soc_is_ar934x())
+ 		ar934x_ip2_irq_init();
++	else if (soc_is_qca953x())
++		qca953x_irq_init();
+ 	else if (soc_is_qca955x())
+ 		qca955x_irq_init();
+ }
 --- a/arch/mips/ath79/setup.c
 +++ b/arch/mips/ath79/setup.c
 @@ -59,6 +59,7 @@ static void __init ath79_detect_sys_type
@@ -329,23 +450,49 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  	pr_info("SoC: %s\n", ath79_sys_type);
 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -105,6 +105,9 @@
+@@ -105,6 +105,21 @@
  #define AR934X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
  #define AR934X_SRIF_SIZE	0x1000
  
++#define QCA953X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
++#define QCA953X_GMAC_SIZE	0x14
 +#define QCA953X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
 +#define QCA953X_WMAC_SIZE	0x20000
++#define QCA953X_EHCI_BASE	0x1b000000
++#define QCA953X_EHCI_SIZE	0x200
++#define QCA953X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
++#define QCA953X_SRIF_SIZE	0x1000
++
++#define QCA953X_PCI_CFG_BASE0	0x14000000
++#define QCA953X_PCI_CTRL_BASE0	(AR71XX_APB_BASE + 0x000f0000)
++#define QCA953X_PCI_CRP_BASE0	(AR71XX_APB_BASE + 0x000c0000)
++#define QCA953X_PCI_MEM_BASE0	0x10000000
++#define QCA953X_PCI_MEM_SIZE	0x02000000
 +
  #define QCA955X_PCI_MEM_BASE0	0x10000000
  #define QCA955X_PCI_MEM_BASE1	0x12000000
  #define QCA955X_PCI_MEM_SIZE	0x02000000
-@@ -279,6 +282,43 @@
+@@ -173,6 +188,12 @@
+ #define AR934X_DDR_REG_FLUSH_PCIE	0xa8
+ #define AR934X_DDR_REG_FLUSH_WMAC	0xac
+ 
++#define QCA953X_DDR_REG_FLUSH_GE0	0x9c
++#define QCA953X_DDR_REG_FLUSH_GE1	0xa0
++#define QCA953X_DDR_REG_FLUSH_USB	0xa4
++#define QCA953X_DDR_REG_FLUSH_PCIE	0xa8
++#define QCA953X_DDR_REG_FLUSH_WMAC	0xac
++
+ /*
+  * PLL block
+  */
+@@ -279,6 +300,44 @@
  
  #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL	BIT(6)
  
 +#define QCA953X_PLL_CPU_CONFIG_REG		0x00
 +#define QCA953X_PLL_DDR_CONFIG_REG		0x04
 +#define QCA953X_PLL_CLK_CTRL_REG		0x08
++#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG	0x24
 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG	0x2c
 +#define QCA953X_PLL_ETH_SGMII_CONTROL_REG	0x48
 +
@@ -356,7 +503,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
-+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK	0x3
++#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK	0x7
 +
 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
@@ -383,27 +530,85 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_PLL_CPU_CONFIG_REG		0x00
  #define QCA955X_PLL_DDR_CONFIG_REG		0x04
  #define QCA955X_PLL_CLK_CTRL_REG		0x08
-@@ -355,6 +395,10 @@
+@@ -355,6 +414,10 @@
  #define AR934X_RESET_REG_BOOTSTRAP		0xb0
  #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac
  
 +#define QCA953X_RESET_REG_RESET_MODULE		0x1c
 +#define QCA953X_RESET_REG_BOOTSTRAP		0xb0
-+#define QCA953X_RESET_REG_EXT_INT_STATUS	0xac
++#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac
 +
  #define QCA955X_RESET_REG_RESET_MODULE		0x1c
  #define QCA955X_RESET_REG_BOOTSTRAP		0xb0
  #define QCA955X_RESET_REG_EXT_INT_STATUS	0xac
-@@ -503,6 +547,8 @@
+@@ -450,6 +513,27 @@
+ #define AR934X_RESET_MBOX		BIT(1)
+ #define AR934X_RESET_I2S		BIT(0)
+ 
++#define QCA953X_RESET_USB_EXT_PWR	BIT(29)
++#define QCA953X_RESET_EXTERNAL		BIT(28)
++#define QCA953X_RESET_RTC		BIT(27)
++#define QCA953X_RESET_FULL_CHIP		BIT(24)
++#define QCA953X_RESET_GE1_MDIO		BIT(23)
++#define QCA953X_RESET_GE0_MDIO		BIT(22)
++#define QCA953X_RESET_CPU_NMI		BIT(21)
++#define QCA953X_RESET_CPU_COLD		BIT(20)
++#define QCA953X_RESET_DDR		BIT(16)
++#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
++#define QCA953X_RESET_GE1_MAC		BIT(13)
++#define QCA953X_RESET_ETH_SWITCH_ANALOG	BIT(12)
++#define QCA953X_RESET_USB_PHY_ANALOG	BIT(11)
++#define QCA953X_RESET_GE0_MAC		BIT(9)
++#define QCA953X_RESET_ETH_SWITCH	BIT(8)
++#define QCA953X_RESET_PCIE_PHY		BIT(7)
++#define QCA953X_RESET_PCIE		BIT(6)
++#define QCA953X_RESET_USB_HOST		BIT(5)
++#define QCA953X_RESET_USB_PHY		BIT(4)
++#define QCA953X_RESET_USBSUS_OVERRIDE	BIT(3)
++
+ #define QCA955X_RESET_HOST		BIT(31)
+ #define QCA955X_RESET_SLIC		BIT(30)
+ #define QCA955X_RESET_HDMA		BIT(29)
+@@ -503,6 +587,13 @@
  #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
  #define AR934X_BOOTSTRAP_DDR1		BIT(0)
  
++#define QCA953X_BOOTSTRAP_SW_OPTION2	BIT(12)
++#define QCA953X_BOOTSTRAP_SW_OPTION1	BIT(11)
++#define QCA953X_BOOTSTRAP_EJTAG_MODE	BIT(5)
 +#define QCA953X_BOOTSTRAP_REF_CLK_40	BIT(4)
++#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
++#define QCA953X_BOOTSTRAP_DDR1		BIT(0)
 +
  #define QCA955X_BOOTSTRAP_REF_CLK_40	BIT(4)
  
  #define AR934X_PCIE_WMAC_INT_WMAC_MISC		BIT(0)
-@@ -565,6 +611,8 @@
+@@ -523,6 +614,24 @@
+ 	 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
+ 	 AR934X_PCIE_WMAC_INT_PCIE_RC3)
+ 
++#define QCA953X_PCIE_WMAC_INT_WMAC_MISC		BIT(0)
++#define QCA953X_PCIE_WMAC_INT_WMAC_TX		BIT(1)
++#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP		BIT(2)
++#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP		BIT(3)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC		BIT(4)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC0		BIT(5)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC1		BIT(6)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC2		BIT(7)
++#define QCA953X_PCIE_WMAC_INT_PCIE_RC3		BIT(8)
++#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
++	(QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
++	 QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
++
++#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
++	(QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
++	 QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
++	 QCA953X_PCIE_WMAC_INT_PCIE_RC3)
++
+ #define QCA955X_EXT_INT_WMAC_MISC		BIT(0)
+ #define QCA955X_EXT_INT_WMAC_TX			BIT(1)
+ #define QCA955X_EXT_INT_WMAC_RXLP		BIT(2)
+@@ -565,6 +674,8 @@
  #define REV_ID_MAJOR_AR9341		0x0120
  #define REV_ID_MAJOR_AR9342		0x1120
  #define REV_ID_MAJOR_AR9344		0x2120
@@ -412,7 +617,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define REV_ID_MAJOR_QCA9556		0x0130
  #define REV_ID_MAJOR_QCA9558		0x1130
  
-@@ -587,6 +635,8 @@
+@@ -587,6 +698,8 @@
  
  #define AR934X_REV_ID_REVISION_MASK	0xf
  
@@ -421,14 +626,81 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
  #define QCA955X_REV_ID_REVISION_MASK	0xf
  
  /*
-@@ -640,6 +690,7 @@
+@@ -634,12 +747,32 @@
+ #define AR934X_GPIO_REG_OUT_FUNC5	0x40
+ #define AR934X_GPIO_REG_FUNC		0x6c
+ 
++#define QCA953X_GPIO_REG_OUT_FUNC0	0x2c
++#define QCA953X_GPIO_REG_OUT_FUNC1	0x30
++#define QCA953X_GPIO_REG_OUT_FUNC2	0x34
++#define QCA953X_GPIO_REG_OUT_FUNC3	0x38
++#define QCA953X_GPIO_REG_OUT_FUNC4	0x3c
++#define QCA953X_GPIO_REG_IN_ENABLE0	0x44
++#define QCA953X_GPIO_REG_FUNC		0x6c
++
++#define QCA953X_GPIO_OUT_MUX_SPI_CS1		10
++#define QCA953X_GPIO_OUT_MUX_SPI_CS2		11
++#define QCA953X_GPIO_OUT_MUX_SPI_CS0		9
++#define QCA953X_GPIO_OUT_MUX_SPI_CLK		8
++#define QCA953X_GPIO_OUT_MUX_SPI_MOSI		12
++#define QCA953X_GPIO_OUT_MUX_LED_LINK1		41
++#define QCA953X_GPIO_OUT_MUX_LED_LINK2		42
++#define QCA953X_GPIO_OUT_MUX_LED_LINK3		43
++#define QCA953X_GPIO_OUT_MUX_LED_LINK4		44
++#define QCA953X_GPIO_OUT_MUX_LED_LINK5		45
++
+ #define AR71XX_GPIO_COUNT		16
+ #define AR7240_GPIO_COUNT		18
+ #define AR7241_GPIO_COUNT		20
  #define AR913X_GPIO_COUNT		22
  #define AR933X_GPIO_COUNT		30
  #define AR934X_GPIO_COUNT		23
-+#define QCA953X_GPIO_COUNT		24
++#define QCA953X_GPIO_COUNT		18
  #define QCA955X_GPIO_COUNT		24
  
  /*
+@@ -663,6 +796,24 @@
+ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT	13
+ #define AR934X_SRIF_DPLL2_OUTDIV_MASK	0x7
+ 
++#define QCA953X_SRIF_CPU_DPLL1_REG	0x1c0
++#define QCA953X_SRIF_CPU_DPLL2_REG	0x1c4
++#define QCA953X_SRIF_CPU_DPLL3_REG	0x1c8
++
++#define QCA953X_SRIF_DDR_DPLL1_REG	0x240
++#define QCA953X_SRIF_DDR_DPLL2_REG	0x244
++#define QCA953X_SRIF_DDR_DPLL3_REG	0x248
++
++#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT	27
++#define QCA953X_SRIF_DPLL1_REFDIV_MASK	0x1f
++#define QCA953X_SRIF_DPLL1_NINT_SHIFT	18
++#define QCA953X_SRIF_DPLL1_NINT_MASK	0x1ff
++#define QCA953X_SRIF_DPLL1_NFRAC_MASK	0x0003ffff
++
++#define QCA953X_SRIF_DPLL2_LOCAL_PLL	BIT(30)
++#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT	13
++#define QCA953X_SRIF_DPLL2_OUTDIV_MASK	0x7
++
+ #define AR71XX_GPIO_FUNC_STEREO_EN		BIT(17)
+ #define AR71XX_GPIO_FUNC_SLIC_EN		BIT(16)
+ #define AR71XX_GPIO_FUNC_SPI_CS2_EN		BIT(13)
+@@ -804,6 +955,16 @@
+ #define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16
+ 
+ /*
++ * QCA953X GMAC Interface
++ */
++#define QCA953X_GMAC_REG_ETH_CFG		0x00
++
++#define QCA953X_ETH_CFG_SW_ONLY_MODE		BIT(6)
++#define QCA953X_ETH_CFG_SW_PHY_SWAP		BIT(7)
++#define QCA953X_ETH_CFG_SW_APB_ACCESS		BIT(9)
++#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST	BIT(13)
++
++/*
+  * QCA955X GMAC Interface
+  */
+ 
 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
 @@ -32,6 +32,7 @@ enum ath79_soc_type {