diff options
| author | John Crispin <john@openwrt.org> | 2016-03-16 09:27:14 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2016-03-16 09:27:14 +0000 |
| commit | 4d6c4994fc609ac40884631ced2d4e4127c8958e (patch) | |
| tree | 6da1e874f0939f02862eee5ccd6a0717dbd122cf /target/linux/ar71xx/files | |
| parent | ebcce35be48abbd948d6c50ac2d1737f4850e028 (diff) | |
| download | upstream-4d6c4994fc609ac40884631ced2d4e4127c8958e.tar.gz upstream-4d6c4994fc609ac40884631ced2d4e4127c8958e.tar.bz2 upstream-4d6c4994fc609ac40884631ced2d4e4127c8958e.zip | |
ar71xx: Use PHY fixups for Open Mesh MR1750
The delays of PHY/MAC on the MR1750 are done by u-boot and OpenWrt in
different ways. u-boot only modifies the ETH_CFG of the QCA955x based on
the link speed. But OpenWrt can only modify the PHY delays based on the
link speed.
This can lead to communication problems when u-boot initializes the ETH_CFG
for a specific link speed (e.g. 10BASE-T) but then OpenWrt the sets the PHY
delays to an incompatible value.
Instead reset the ETH_CFG delay bits of the QCA955x to a specific value and
only rely on the AT803x PHY settings.
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
SVN-Revision: 49031
Diffstat (limited to 'target/linux/ar71xx/files')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c | 25 |
1 files changed, 22 insertions, 3 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c index 8db291509f..83acd4cc34 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c @@ -22,6 +22,7 @@ #include <linux/ar8216_platform.h> #include <asm/mach-ath79/ar71xx_regs.h> +#include <linux/platform_data/phy-at803x.h> #include "common.h" #include "dev-ap9x-pci.h" @@ -92,14 +93,29 @@ static struct gpio_keys_button mr1750_gpio_keys[] __initdata = { }, }; +static struct at803x_platform_data mr1750_at803x_data = { + .disable_smarteee = 1, + .enable_rgmii_rx_delay = 1, + .enable_rgmii_tx_delay = 0, + .fixup_rgmii_tx_delay = 1, +}; + +static struct mdio_board_info mr1750_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 5, + .platform_data = &mr1750_at803x_data, + }, +}; + static void __init mr1750_setup(void) { u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); u8 mac[6]; - ath79_eth0_pll_data.pll_1000 = 0xbe000101; - ath79_eth0_pll_data.pll_100 = 0x80000101; - ath79_eth0_pll_data.pll_10 = 0x80001313; + ath79_eth0_pll_data.pll_1000 = 0xae000000; + ath79_eth0_pll_data.pll_100 = 0xa0000101; + ath79_eth0_pll_data.pll_10 = 0xa0001313; ath79_register_m25p80(NULL); @@ -116,6 +132,9 @@ static void __init mr1750_setup(void) ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0); ath79_register_mdio(0, 0x0); + mdiobus_register_board_info(mr1750_mdio0_info, + ARRAY_SIZE(mr1750_mdio0_info)); + ath79_init_mac(ath79_eth0_data.mac_addr, art + MR1750_MAC0_OFFSET, 0); /* GMAC0 is connected to the RMGII interface */ |