ar71xx: add support for P&W R602N and CPE505N

P&W (full name: Shenzhen Progress&Win Technologies) R602N (could be also
labeled as R602F, R602, etc.) is a simple N300 router with 5-port
10/100 Mbps switch, non-detachable antennas and USB.

CPE505 is an outdoor CPE with PoE support and detachable antennas.

Both devices are based on Qualcomm/Atheros QCA9531 v2.

Common specification:

- 650/597/216 MHz (CPU/DDR/AHB)
- 64 MB of RAM (DDR2)
- 16 MB of FLASH
- UART (J2) header on PCB

R602N specification:

- 5x 10/100 Mbps Ethernet
- 1x USB 2.0
- 2T2R 2.4 GHz with external LNA and PA (SE2576L), up to 28 dBm
- 2x external, non-detachable antennas
- 7x LED, 1x button

CPE505N specification:

- 2x 10/100 Mbps Ethernet (both ports support passive PoE 12-24 V)
- 2T2R 2.4 GHz with external LNA and PA (SKY65174-21), up to 30 dBm
- 2x external, detachable antennas (RP-SMA connectors)
- 1x RGB LED, 2x LEDs (in RJ45 sockets), 1x button

Flash instructions:

It seems that there are many different versions of the firmware which
these devices are shipped with. The generic/standard one is based on
some modified OpenWrt and LEDE firmware can be flashed directly from
vendor's webgui or with sysupgrade (root password is "admin123").

Before flashing, make sure (use "fw_printenv") that the kernel load
address in your device is set to "0x9f050000" (bootcmd variable is
"bootm 0x9f050000"). If your device uses different load address, you
should first change it, under vendor's firmware, with command:

fw_setenv bootcmd "bootm 0x9f050000 || bootm OLD_ADDRESS"

Where OLD_ADDRESS is previous kernel load address (in CPE505 version
I got access to, it was "0x9fe80000"). This will allow you to use
both the vendor's and LEDE firmware.

If version of your device contains empty U-Boot environment (you will
get information about this after issuing "fw_printenv"), you should
use U-Boot, serial line access and TFTP to perform firmware upgrade:

1. tftp 0x80060000 lede-ar71xx-generic-...-squashfs-sysupgrade.bin
2. erase 0x9f050000 +$filesize
3. cp.b $fileaddr 0x9f050000 $filesize
4. setenv bootcmd "bootm 0x9f050000 || bootm OLD_ADDRESS"
5. saveenv && reset

These devices contain also web recovery mode inside U-Boot. It can be
started with pressing the reset button for around 3 seconds just after
the device powerup. Web recovery panel is available on "192.168.10.9"
and to be able to use it, IP on your PC must be set to "192.168.10.10".

Make sure to change kernel load address before using recovery mode or
the U-Boot will not be able to load LEDE firmware.

Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>

4 files changed, 236 insertions, 0 deletions

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt b/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt
index d72c462f6e..669e02684f 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt
+++ b/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt
@@ -851,6 +851,16 @@ config ATH79_MACH_WRTNODE2Q
 	select ATH79_DEV_M25P80
 	select ATH79_DEV_WMAC
 
+config ATH79_MACH_R602N
+	bool "P&W R602N support"
+	select SOC_QCA953X
+	select ATH79_DEV_ETH
+	select ATH79_DEV_GPIO_BUTTONS
+	select ATH79_DEV_LEDS_GPIO
+	select ATH79_DEV_M25P80
+	select ATH79_DEV_USB
+	select ATH79_DEV_WMAC
+
 config ATH79_MACH_R6100
 	bool "NETGEAR R6100 board support"
 	select SOC_AR934X
@@ -1308,6 +1318,15 @@ config ATH79_MACH_ARCHER_C7
 	select ATH79_DEV_USB
 	select ATH79_DEV_WMAC
 
+config ATH79_MACH_CPE505N
+	bool "P&W CPE505N support"
+	select SOC_QCA953X
+	select ATH79_DEV_ETH
+	select ATH79_DEV_GPIO_BUTTONS
+	select ATH79_DEV_LEDS_GPIO
+	select ATH79_DEV_M25P80
+	select ATH79_DEV_WMAC
+
 config ATH79_MACH_CPE510
 	bool "TP-LINK CPE510 support"
 	select SOC_AR934X
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/Makefile b/target/linux/ar71xx/files/arch/mips/ath79/Makefile
index 7e1a71b34d..1180d4d73b 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/Makefile
+++ b/target/linux/ar71xx/files/arch/mips/ath79/Makefile
@@ -75,6 +75,7 @@ obj-$(CONFIG_ATH79_MACH_CF_E380AC_V1)		+= mach-cf-e316n-v2.o
 obj-$(CONFIG_ATH79_MACH_CF_E380AC_V2)		+= mach-cf-e316n-v2.o
 obj-$(CONFIG_ATH79_MACH_CF_E520N)		+= mach-cf-e316n-v2.o
 obj-$(CONFIG_ATH79_MACH_CF_E530N)		+= mach-cf-e316n-v2.o
+obj-$(CONFIG_ATH79_MACH_CPE505N)		+= mach-r602n.o
 obj-$(CONFIG_ATH79_MACH_CPE510)			+= mach-cpe510.o
 obj-$(CONFIG_ATH79_MACH_CPE830)			+= mach-ap90q.o
 obj-$(CONFIG_ATH79_MACH_CPE870)			+= mach-cpe870.o
@@ -147,6 +148,7 @@ obj-$(CONFIG_ATH79_MACH_PB42)			+= mach-pb42.o
 obj-$(CONFIG_ATH79_MACH_PB44)			+= mach-pb44.o
 obj-$(CONFIG_ATH79_MACH_PQI_AIR_PEN)		+= mach-pqi-air-pen.o
 obj-$(CONFIG_ATH79_MACH_QIHOO_C301)		+= mach-qihoo-c301.o
+obj-$(CONFIG_ATH79_MACH_R602N)			+= mach-r602n.o
 obj-$(CONFIG_ATH79_MACH_R6100)			+= mach-r6100.o
 obj-$(CONFIG_ATH79_MACH_RB2011)			+= mach-rb2011.o
 obj-$(CONFIG_ATH79_MACH_RB4XX)			+= mach-rb4xx.o
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-r602n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-r602n.c
new file mode 100644
index 0000000000..4aef0a932a
--- /dev/null
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-r602n.c
@@ -0,0 +1,213 @@
+/*
+ * P&W (Shenzhen Progress&Win Technologies) R602N and CPE505N boards support
+ *
+ * Copyright (C) 2017 Piotr Dymacz <pepe2k@gmail.com>
+ *
+ * Based on mach-zbt-we1526.c
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/ar71xx_regs.h>
+
+#include "common.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+
+#define PW_GPIO_BTN_RESET	17
+
+#define PW_KEYS_POLL_INTERVAL		20 /* msecs */
+#define PW_KEYS_DEBOUNCE_INTERVAL	(3 * PW_KEYS_POLL_INTERVAL)
+
+#define PW_MAC0_OFFSET		0x0
+#define PW_MAC1_OFFSET		0x6
+#define PW_WMAC_CALDATA_OFFSET	0x1000
+
+/* CPE505N GPIO LEDs */
+#define CPE505N_GPIO_LED_DIAG	12
+#define CPE505N_GPIO_LED_LAN	11
+#define CPE505N_GPIO_LED_STATUS	14
+#define CPE505N_GPIO_LED_WAN	4
+#define CPE505N_GPIO_LED_WLAN	15
+
+static struct gpio_led cpe505n_leds_gpio[] __initdata = {
+	{
+		.name		= "cpe505n:red:diag",
+		.gpio		= CPE505N_GPIO_LED_DIAG,
+		.active_low	= 1,
+	}, {
+		.name		= "cpe505n:green:lan",
+		.gpio		= CPE505N_GPIO_LED_LAN,
+		.active_low	= 1,
+	}, {
+		.name		= "cpe505n:green:status",
+		.gpio		= CPE505N_GPIO_LED_STATUS,
+		.active_low	= 1,
+	}, {
+		.name		= "cpe505n:green:wan",
+		.gpio		= CPE505N_GPIO_LED_WAN,
+		.active_low	= 1,
+	}, {
+		.name		= "cpe505n:blue:wlan",
+		.gpio		= CPE505N_GPIO_LED_WLAN,
+		.active_low	= 1,
+	},
+};
+
+static void __init cpe505n_gpio_setup(void)
+{
+	/* For LED on GPIO4 */
+	ath79_gpio_function_disable(AR934X_GPIO_FUNC_CLK_OBS4_EN);
+	ath79_gpio_output_select(CPE505N_GPIO_LED_WAN, 0);
+
+	ath79_gpio_direction_select(CPE505N_GPIO_LED_DIAG, true);
+	ath79_gpio_direction_select(CPE505N_GPIO_LED_LAN, true);
+	ath79_gpio_direction_select(CPE505N_GPIO_LED_STATUS, true);
+	ath79_gpio_direction_select(CPE505N_GPIO_LED_WAN, true);
+	ath79_gpio_direction_select(CPE505N_GPIO_LED_WLAN, true);
+
+	/* Mute LEDs */
+	gpio_set_value(CPE505N_GPIO_LED_DIAG, 1);
+	gpio_set_value(CPE505N_GPIO_LED_LAN, 1);
+	gpio_set_value(CPE505N_GPIO_LED_STATUS, 1);
+	gpio_set_value(CPE505N_GPIO_LED_WAN, 1);
+	gpio_set_value(CPE505N_GPIO_LED_WLAN, 1);
+
+	ath79_register_leds_gpio(-1, ARRAY_SIZE(cpe505n_leds_gpio),
+				 cpe505n_leds_gpio);
+}
+
+/* R602N GPIO LEDs */
+#define R602N_GPIO_LED_LAN1	16
+#define R602N_GPIO_LED_LAN2	15
+#define R602N_GPIO_LED_LAN3	14
+#define R602N_GPIO_LED_LAN4	11
+#define R602N_GPIO_LED_WAN	4
+#define R602N_GPIO_LED_WLAN	12
+
+static struct gpio_led r602n_leds_gpio[] __initdata = {
+	{
+		.name		= "r602n:green:lan1",
+		.gpio		= R602N_GPIO_LED_LAN1,
+		.active_low	= 1,
+	}, {
+		.name		= "r602n:green:lan2",
+		.gpio		= R602N_GPIO_LED_LAN2,
+		.active_low	= 1,
+	}, {
+		.name		= "r602n:green:lan3",
+		.gpio		= R602N_GPIO_LED_LAN3,
+		.active_low	= 1,
+	}, {
+		.name		= "r602n:green:lan4",
+		.gpio		= R602N_GPIO_LED_LAN4,
+		.active_low	= 1,
+	}, {
+		.name		= "r602n:green:wan",
+		.gpio		= R602N_GPIO_LED_WAN,
+		.active_low	= 1,
+	}, {
+		.name		= "r602n:green:wlan",
+		.gpio		= R602N_GPIO_LED_WLAN,
+		.active_low	= 1,
+	},
+};
+
+static void __init r602n_gpio_setup(void)
+{
+	/* For LED on GPIO4 */
+	ath79_gpio_function_disable(AR934X_GPIO_FUNC_CLK_OBS4_EN);
+	ath79_gpio_output_select(R602N_GPIO_LED_WAN, 0);
+
+	ath79_gpio_direction_select(R602N_GPIO_LED_LAN1, true);
+	ath79_gpio_direction_select(R602N_GPIO_LED_LAN2, true);
+	ath79_gpio_direction_select(R602N_GPIO_LED_LAN3, true);
+	ath79_gpio_direction_select(R602N_GPIO_LED_LAN4, true);
+	ath79_gpio_direction_select(R602N_GPIO_LED_WAN, true);
+	ath79_gpio_direction_select(R602N_GPIO_LED_WLAN, true);
+
+	/* Mute LEDs */
+	gpio_set_value(R602N_GPIO_LED_LAN1, 1);
+	gpio_set_value(R602N_GPIO_LED_LAN2, 1);
+	gpio_set_value(R602N_GPIO_LED_LAN3, 1);
+	gpio_set_value(R602N_GPIO_LED_LAN4, 1);
+	gpio_set_value(R602N_GPIO_LED_WAN, 1);
+	gpio_set_value(R602N_GPIO_LED_WLAN, 1);
+
+	ath79_register_leds_gpio(-1, ARRAY_SIZE(r602n_leds_gpio),
+				 r602n_leds_gpio);
+}
+
+static struct gpio_keys_button pw_gpio_keys[] __initdata = {
+	{
+		.desc		= "reset",
+		.type		= EV_KEY,
+		.code		= KEY_RESTART,
+		.debounce_interval = PW_KEYS_DEBOUNCE_INTERVAL,
+		.gpio		= PW_GPIO_BTN_RESET,
+		.active_low	= 1,
+	},
+};
+
+static void __init r602n_cpe505n_setup(void)
+{
+	u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+
+	ath79_register_m25p80(NULL);
+
+	ath79_setup_ar933x_phy4_switch(false, false);
+
+	ath79_register_mdio(0, 0x0);
+
+	/* LAN */
+	ath79_eth1_data.duplex = DUPLEX_FULL;
+	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
+	ath79_switch_data.phy_poll_mask |= BIT(4);
+	ath79_init_mac(ath79_eth1_data.mac_addr, art + PW_MAC1_OFFSET, 0);
+	ath79_register_eth(1);
+
+	/* WAN */
+	ath79_switch_data.phy4_mii_en = 1;
+	ath79_eth0_data.duplex = DUPLEX_FULL;
+	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+	ath79_eth0_data.phy_mask = BIT(4);
+	ath79_eth0_data.speed = SPEED_100;
+	ath79_init_mac(ath79_eth0_data.mac_addr, art + PW_MAC0_OFFSET, 0);
+	ath79_register_eth(0);
+
+	ath79_register_wmac(art + PW_WMAC_CALDATA_OFFSET, NULL);
+
+	ath79_register_gpio_keys_polled(-1, PW_KEYS_POLL_INTERVAL,
+					ARRAY_SIZE(pw_gpio_keys),
+					pw_gpio_keys);
+}
+
+static void __init cpe505n_setup(void)
+{
+	r602n_cpe505n_setup();
+
+	cpe505n_gpio_setup();
+}
+
+static void __init r602n_setup(void)
+{
+	r602n_cpe505n_setup();
+
+	r602n_gpio_setup();
+
+	ath79_register_usb();
+}
+
+MIPS_MACHINE(ATH79_MACH_CPE505N, "CPE505N", "P&W CPE505N", cpe505n_setup);
+MIPS_MACHINE(ATH79_MACH_R602N, "R602N", "P&W R602N", r602n_setup);
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h b/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h
index 27ebd47f29..b9cc243f39 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h
+++ b/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h
@@ -62,6 +62,7 @@ enum ath79_mach_type {
 	ATH79_MACH_CF_E520N,			/* COMFAST CF-E520N */
 	ATH79_MACH_CF_E530N,			/* COMFAST CF-E530N */
 	ATH79_MACH_CPE210,			/* TP-LINK CPE210 */
+	ATH79_MACH_CPE505N,			/* P&W CPE505N */
 	ATH79_MACH_CPE510,			/* TP-LINK CPE510 */
 	ATH79_MACH_CPE830,			/* YunCore CPE830 */
 	ATH79_MACH_CPE870,			/* YunCore CPE870 */
@@ -152,6 +153,7 @@ enum ath79_mach_type {
 	ATH79_MACH_PB44,			/* Atheros PB44 reference board */
 	ATH79_MACH_PQI_AIR_PEN,			/* PQI Air Pen */
 	ATH79_MACH_QIHOO_C301,			/* Qihoo 360 C301 */
+	ATH79_MACH_R602N,			/* P&W R602N */
 	ATH79_MACH_R6100,			/* NETGEAR R6100 */
 	ATH79_MACH_RB_2011G,			/* Mikrotik RouterBOARD 2011UAS-2HnD */
 	ATH79_MACH_RB_2011L,			/* Mikrotik RouterBOARD 2011L */